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################################################################################
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#
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#
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# Copyright 2013, Sinclair R.F., Inc.
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# Copyright 2013-2014, Sinclair R.F., Inc.
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#
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#
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################################################################################
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################################################################################
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import math;
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import math;
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import re;
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import re;
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from ssbccPeripheral import SSBCCperipheral
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from ssbccPeripheral import SSBCCperipheral
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from ssbccUtil import CeilLog2;
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from ssbccUtil import CeilLog2;
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from ssbccUtil import IsPowerOf2;
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from ssbccUtil import IsPowerOf2;
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from ssbccUtil import SSBCCException;
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from ssbccUtil import SSBCCException;
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class inFIFO_async(SSBCCperipheral):
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class inFIFO_async(SSBCCperipheral):
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"""
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"""
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Input FIFO with an asynchronous clock.\n
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Input FIFO with an asynchronous clock.\n
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Usage:
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Usage:
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PERIPHERAL inFIFO_async inclk=<i_clock> \\
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PERIPHERAL inFIFO_async inclk=<i_clock> \\
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data=<i_data> \\
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data=<i_data> \\
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data_wr=<i_data_wr> \\
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data_wr=<i_data_wr> \\
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data_full=<o_data_full> \\
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data_full=<o_data_full> \\
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inport=<I_data> \\
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inport=<I_data> \\
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inempty=<I_empty> \\
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inempty=<I_empty> \\
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depth=<N> \n
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depth=<N> \n
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Where:
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Where:
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inclk=<i_clock>
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inclk=<i_clock>
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specifies the name of the asynchronous clock
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specifies the name of the asynchronous clock
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data=<i_data>
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data=<i_data>
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specifies the name of the 8-bit incoming data
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specifies the name of the 8-bit incoming data
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data_wr=<i_data_wr>
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data_wr=<i_data_wr>
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specifies the name if the write strobe
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specifies the name if the write strobe
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data_full=<o_data_full>
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data_full=<o_data_full>
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specifies the name of the output "full" status of the FIFO
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specifies the name of the output "full" status of the FIFO
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inport=<I_data>
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inport=<I_data>
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specifies the name of the port to read from the FIFO
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specifies the name of the port to read from the FIFO
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inempty=<I_empty>
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inempty=<I_empty>
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specifies the symbol used by the inport instruction to read the "empty"
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specifies the symbol used by the inport instruction to read the "empty"
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status of the FIFO
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status of the FIFO
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depth=<N>
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depth=<N>
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specifies the depth of the FIFO
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specifies the depth of the FIFO
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Note: N must be a power of 2 and must be at least 16.\n
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Note: N must be a power of 2 and must be at least 16.\n
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Example: Provide a FIFO for an external device or IP that pushes 8-bit data
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Example: Provide a FIFO for an external device or IP that pushes 8-bit data
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to the processor.\n
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to the processor.\n
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The PERIPHERAL statement would be:\n
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The PERIPHERAL statement would be:\n
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PERIPHERAL inFIFO_async inclk=i_dev_clk \\
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PERIPHERAL inFIFO_async inclk=i_dev_clk \\
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data=i_dev_data \\
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data=i_dev_data \\
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data_wr=i_dev_data_wr \\
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data_wr=i_dev_data_wr \\
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data_full=o_dev_full \\
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data_full=o_dev_full \\
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inport=I_DATA_FIFO \\
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inport=I_DATA_FIFO \\
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inempty=I_DATA_FIFO_EMPTY \\
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inempty=I_DATA_FIFO_EMPTY \\
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depth=32\n
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depth=32\n
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To read from the FIFO and store the values on the data stack until the FIFO
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To read from the FIFO and store the values on the data stack until the FIFO
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is empty and to track the number of values received, do the following:\n
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is empty and to track the number of values received, do the following:\n
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; ( - u_first ... u_last u_N )
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; ( - u_first ... u_last u_N )
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0x00 :loop
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0x00 :loop
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.inport(I_DATA_FIFO_EMPTY) .jumpc(done)
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.inport(I_DATA_FIFO_EMPTY) .jumpc(done)
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.inport(I_DATA_FIFO) swap
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.inport(I_DATA_FIFO) swap
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.jump(loop,1+)
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.jump(loop,1+)
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:done
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:done
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"""
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"""
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def __init__(self,peripheralFile,config,param_list,loc):
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def __init__(self,peripheralFile,config,param_list,loc):
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# Use the externally provided file name for the peripheral
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# Use the externally provided file name for the peripheral
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self.peripheralFile = peripheralFile;
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self.peripheralFile = peripheralFile;
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# Get the parameters.
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# Get the parameters.
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allowables = (
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allowables = (
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('inclk', r'i_\w+$', None, ),
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( 'inclk', r'i_\w+$', None, ),
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('data', r'i_\w+$', None, ),
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( 'data', r'i_\w+$', None, ),
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('data_wr', r'i_\w+$', None, ),
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( 'data_wr', r'i_\w+$', None, ),
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('data_full', r'o_\w+$', None, ),
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( 'data_full', r'o_\w+$', None, ),
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('inport', r'I_\w+$', None, ),
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( 'inport', r'I_\w+$', None, ),
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('inempty', r'I_\w+$', None, ),
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('inempty', r'I_\w+$', None, ),
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('depth', r'[1-9]\d*$', int, ),
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( 'depth', r'[1-9]\d*$', lambda v : self.IntPow2(v,minValue=16), ),
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);
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);
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names = [a[0] for a in allowables];
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names = [a[0] for a in allowables];
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for param_tuple in param_list:
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for param_tuple in param_list:
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param = param_tuple[0];
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param = param_tuple[0];
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if param not in names:
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if param not in names:
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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raise SSBCCException('Unrecognized parameter "%s" at %s' % (param,loc,));
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param_test = allowables[names.index(param)];
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param_test = allowables[names.index(param)];
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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self.AddAttr(config,param,param_tuple[1],param_test[1],loc,param_test[2]);
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# Ensure the required parameters are provided.
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# Ensure the required parameters are provided.
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for paramname in names:
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for paramname in names:
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if not hasattr(self,paramname):
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if not hasattr(self,paramname):
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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raise SSBCCException('Required parameter "%s" is missing at %s' % (paramname,loc,));
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# Ensure the depth is a power of 2.
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if not IsPowerOf2(self.depth):
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raise SSBCCException('depth=%d must be a power of 2 at %s' % (self.depth,loc,));
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if self.depth < 16:
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raise SSBCCException('depth=%d must be at least 16 at %s' % (self.depth,loc,));
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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# Add the I/O port, internal signals, and the INPORT and OUTPORT symbols for this peripheral.
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config.AddIO(self.inclk,1,'input',loc);
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config.AddIO(self.inclk,1,'input',loc);
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config.AddIO(self.data,8,'input',loc);
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config.AddIO(self.data,8,'input',loc);
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config.AddIO(self.data_wr,1,'input',loc);
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config.AddIO(self.data_wr,1,'input',loc);
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config.AddIO(self.data_full,1,'output',loc);
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config.AddIO(self.data_full,1,'output',loc);
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config.AddSignal('s__%s__data' % self.data,8,loc);
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config.AddSignal('s__%s__data' % self.data,8,loc);
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config.AddSignal('s__%s__empty' % self.data,1,loc);
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config.AddSignal('s__%s__empty' % self.data,1,loc);
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self.ix_data = config.NInports();
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self.ix_data = config.NInports();
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config.AddInport((self.inport,
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config.AddInport((self.inport,
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('s__%s__data' % self.data,8,'data',),
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('s__%s__data' % self.data,8,'data',),
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),loc);
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),loc);
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config.AddInport((self.inempty,
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config.AddInport((self.inempty,
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('s__%s__empty' % self.data,1,'data',),
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('s__%s__empty' % self.data,1,'data',),
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),loc);
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),loc);
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def GenVerilog(self,fp,config):
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def GenVerilog(self,fp,config):
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body = self.LoadCore(self.peripheralFile,'.v');
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body = self.LoadCore(self.peripheralFile,'.v');
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for subpair in (
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for subpair in (
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(r'@DATA@', self.data, ),
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( r'@DATA@', self.data, ),
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(r'@DATA_FULL@', self.data_full, ),
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( r'@DATA_FULL@', self.data_full, ),
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(r'@DATA_WR@', self.data_wr, ),
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( r'@DATA_WR@', self.data_wr, ),
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(r'@DEPTH@', str(self.depth), ),
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( r'@DEPTH@', str(self.depth), ),
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(r'@DEPTH-1@', str(self.depth-1), ),
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( r'@DEPTH-1@', str(self.depth-1), ),
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(r'@DEPTH_NBITS@', str(CeilLog2(self.depth)), ),
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( r'@DEPTH_NBITS@', str(CeilLog2(self.depth)), ),
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(r'@DEPTH_NBITS-1@', str(CeilLog2(self.depth)-1), ),
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( r'@DEPTH_NBITS-1@', str(CeilLog2(self.depth)-1), ),
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(r'@INCLK@', self.inclk, ),
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( r'@INCLK@', self.inclk, ),
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(r'@IX_DATA@', str(self.ix_data), ),
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( r'@IX_DATA@', str(self.ix_data), ),
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(r'@NAME@', self.data, ),
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( r'@NAME@', self.data, ),
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(r'\bgen__', 'gen__%s__' % self.data, ),
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( r'\bgen__', 'gen__%s__' % self.data, ),
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(r'\bix__', 'ix__%s__' % self.data, ),
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( r'\bix__', 'ix__%s__' % self.data, ),
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(r'\bs__', 's__%s__' % self.data, ),
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( r'\bs__', 's__%s__' % self.data, ),
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):
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):
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body = re.sub(subpair[0],subpair[1],body);
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body = re.sub(subpair[0],subpair[1],body);
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body = self.GenVerilogFinal(config,body);
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body = self.GenVerilogFinal(config,body);
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fp.write(body);
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fp.write(body);
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