//
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//
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// PERIPHERAL inFIFO_async: @NAME@
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// PERIPHERAL inFIFO_async: @NAME@
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// Copyright 2014, Sinclair R.F., Inc.
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//
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//
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generate
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generate
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// FIFO memory
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// FIFO memory
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reg [7:0] s__fifo[@DEPTH-1@:0];
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reg [7:0] s__fifo[@DEPTH-1@:0];
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// write side of the FIFO
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// write side of the FIFO
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reg [@DEPTH_NBITS-1@:0] s__ix_in = @DEPTH_NBITS@'h0;
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reg [@DEPTH_NBITS-1@:0] s__ix_in = @DEPTH_NBITS@'h0;
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always @ (posedge i_rst or posedge @INCLK@)
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always @ (posedge i_rst or posedge @INCLK@)
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if (i_rst)
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if (i_rst)
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s__ix_in <= @DEPTH_NBITS@'h0;
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s__ix_in <= @DEPTH_NBITS@'h0;
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else if (@DATA_WR@) begin
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else if (@DATA_WR@) begin
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s__ix_in <= s__ix_in + @DEPTH_NBITS@'d1;
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s__ix_in <= s__ix_in + @DEPTH_NBITS@'d1;
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s__fifo[s__ix_in] <= @DATA@;
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s__fifo[s__ix_in] <= @DATA@;
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end else
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end else
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s__ix_in <= s__ix_in;
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s__ix_in <= s__ix_in;
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// read side of the FIFO
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// read side of the FIFO
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reg [@DEPTH_NBITS-1@:0] s__ix_out = @DEPTH_NBITS@'h0;
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reg [@DEPTH_NBITS-1@:0] s__ix_out = @DEPTH_NBITS@'h0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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if (i_rst)
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if (i_rst)
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s__ix_out <= @DEPTH_NBITS@'h0;
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s__ix_out <= @DEPTH_NBITS@'h0;
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else if (s_inport && (s_T == 8'd@IX_DATA@))
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else if (s_inport && (s_T == 8'd@IX_DATA@))
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s__ix_out <= s__ix_out + @DEPTH_NBITS@'d1;
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s__ix_out <= s__ix_out + @DEPTH_NBITS@'d1;
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else
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else
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s__ix_out <= s__ix_out;
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s__ix_out <= s__ix_out;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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s__data <= s__fifo[s__ix_out];
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s__data <= s__fifo[s__ix_out];
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// empty indication to the micro controller
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// empty indication to the micro controller
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// Note: The lag in the "empty" indication is OK because of the minimum 2 clock
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// Note: The lag in the "empty" indication is OK because of the minimum 2 clock
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// delay between reading the data and then reading the "empty"
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// delay between reading the data and then reading the "empty"
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// indication.
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// indication.
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reg [@DEPTH_NBITS-1@:0] s__ix_in_gray = @DEPTH_NBITS@'h0;
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reg [@DEPTH_NBITS-1@:0] s__ix_in_gray = @DEPTH_NBITS@'h0;
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always @ (posedge @INCLK@)
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always @ (posedge @INCLK@)
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s__ix_in_gray <= { 1'b0, s__ix_in[@DEPTH_NBITS-1@:1] } ^ s__ix_in;
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s__ix_in_gray <= { 1'b0, s__ix_in[@DEPTH_NBITS-1@:1] } ^ s__ix_in;
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reg [@DEPTH_NBITS-1@:0] s__ix_in_gray_s[2:0];
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reg [@DEPTH_NBITS-1@:0] s__ix_in_gray_s[2:0];
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always @ (posedge i_clk) begin
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always @ (posedge i_clk) begin
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s__ix_in_gray_s[0] <= s__ix_in_gray;
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s__ix_in_gray_s[0] <= s__ix_in_gray;
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s__ix_in_gray_s[1] <= s__ix_in_gray_s[0];
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s__ix_in_gray_s[1] <= s__ix_in_gray_s[0];
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s__ix_in_gray_s[2] <= s__ix_in_gray_s[1];
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s__ix_in_gray_s[2] <= s__ix_in_gray_s[1];
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end
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end
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genvar ix__clk;
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genvar ix__clk;
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wire [@DEPTH_NBITS-1@:0] s__ix_in_clk;
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wire [@DEPTH_NBITS-1@:0] s__ix_in_clk;
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assign s__ix_in_clk[@DEPTH_NBITS-1@] = s__ix_in_gray_s[2][@DEPTH_NBITS-1@];
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assign s__ix_in_clk[@DEPTH_NBITS-1@] = s__ix_in_gray_s[2][@DEPTH_NBITS-1@];
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for (ix__clk=@DEPTH_NBITS-1@; ix__clk>0; ix__clk=ix__clk-1) begin : gen__ix_in_clk
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for (ix__clk=@DEPTH_NBITS-1@; ix__clk>0; ix__clk=ix__clk-1) begin : gen__ix_in_clk
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assign s__ix_in_clk[ix__clk-1] = s__ix_in_clk[ix__clk] ^ s__ix_in_gray_s[2][ix__clk-1];
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assign s__ix_in_clk[ix__clk-1] = s__ix_in_clk[ix__clk] ^ s__ix_in_gray_s[2][ix__clk-1];
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end
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end
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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s__empty <= (s__ix_in_clk == s__ix_out);
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s__empty <= (s__ix_in_clk == s__ix_out);
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// full indication to the fabric
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// full indication to the fabric
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reg [@DEPTH_NBITS-1@:0] s__ix_out_gray = @DEPTH_NBITS@'h0;
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reg [@DEPTH_NBITS-1@:0] s__ix_out_gray = @DEPTH_NBITS@'h0;
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always @ (posedge i_clk)
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always @ (posedge i_clk)
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s__ix_out_gray <= { 1'b0, s__ix_out[@DEPTH_NBITS-1@:1] } ^ s__ix_out;
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s__ix_out_gray <= { 1'b0, s__ix_out[@DEPTH_NBITS-1@:1] } ^ s__ix_out;
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reg [@DEPTH_NBITS-1@:0] s__ix_out_gray_s[2:0];
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reg [@DEPTH_NBITS-1@:0] s__ix_out_gray_s[2:0];
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always @ (posedge @INCLK@) begin
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always @ (posedge @INCLK@) begin
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s__ix_out_gray_s[0] <= s__ix_out_gray;
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s__ix_out_gray_s[0] <= s__ix_out_gray;
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s__ix_out_gray_s[1] <= s__ix_out_gray_s[0];
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s__ix_out_gray_s[1] <= s__ix_out_gray_s[0];
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s__ix_out_gray_s[2] <= s__ix_out_gray_s[1];
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s__ix_out_gray_s[2] <= s__ix_out_gray_s[1];
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end
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end
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genvar ix__inclk;
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genvar ix__inclk;
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wire [@DEPTH_NBITS-1@:0] s__ix_out_inclk;
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wire [@DEPTH_NBITS-1@:0] s__ix_out_inclk;
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assign s__ix_out_inclk[@DEPTH_NBITS-1@] = s__ix_out_gray_s[2][@DEPTH_NBITS-1@];
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assign s__ix_out_inclk[@DEPTH_NBITS-1@] = s__ix_out_gray_s[2][@DEPTH_NBITS-1@];
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for (ix__inclk=@DEPTH_NBITS-1@; ix__inclk>0; ix__inclk=ix__inclk-1) begin : gen__ix_out_inclk
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for (ix__inclk=@DEPTH_NBITS-1@; ix__inclk>0; ix__inclk=ix__inclk-1) begin : gen__ix_out_inclk
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assign s__ix_out_inclk[ix__inclk-1] = s__ix_out_inclk[ix__inclk] ^ s__ix_out_gray_s[2][ix__inclk-1];
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assign s__ix_out_inclk[ix__inclk-1] = s__ix_out_inclk[ix__inclk] ^ s__ix_out_gray_s[2][ix__inclk-1];
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end
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end
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reg [@DEPTH_NBITS-1@:0] s__delta_inclk = @DEPTH_NBITS@'h0;
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reg [@DEPTH_NBITS-1@:0] s__delta_inclk = @DEPTH_NBITS@'h0;
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always @ (posedge @INCLK@)
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always @ (posedge @INCLK@)
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s__delta_inclk <= s__ix_in - s__ix_out_inclk;
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s__delta_inclk <= s__ix_in - s__ix_out_inclk;
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always @ (posedge @INCLK@)
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always @ (posedge @INCLK@)
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@DATA_FULL@ <= &s__delta_inclk[@DEPTH_NBITS-1@:3];
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@DATA_FULL@ <= &s__delta_inclk[@DEPTH_NBITS-1@:3];
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endgenerate
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endgenerate
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