/*******************************************************************************
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/*******************************************************************************
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*
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*
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* Copyright 2013, Sinclair R.F., Inc.
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* Copyright 2013, Sinclair R.F., Inc.
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*
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*
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* Test bench for the AXI4-Lite slave dual-port-ram peripheral.
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* Test bench for the AXI4-Lite slave dual-port-ram peripheral.
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*
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*
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******************************************************************************/
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******************************************************************************/
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`timescale 1ns/1ps
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`timescale 1ns/1ps
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module tb;
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module tb;
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// 125 MHz clock
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// 125 MHz clock
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reg s_clk = 1'b1;
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reg s_clk = 1'b1;
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always @ (s_clk)
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always @ (s_clk)
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s_clk <= #4 ~s_clk;
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s_clk <= #4 ~s_clk;
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reg s_rst = 1'b1;
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reg s_rst = 1'b1;
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initial begin
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initial begin
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repeat (5) @ (posedge s_clk);
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repeat (5) @ (posedge s_clk);
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s_rst = 1'b0;
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s_rst = 1'b0;
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end
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end
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//
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//
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// Simulate the AXI4-Lite master
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// Simulate the AXI4-Lite master
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//
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//
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reg s_aclk = 1'b1;
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reg s_aclk = 1'b1;
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always @ (s_aclk)
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always @ (s_aclk)
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s_aclk <= #5 ~s_aclk;
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s_aclk <= #5 ~s_aclk;
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// Command AXI4-Lite writes and reads.
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// Command AXI4-Lite writes and reads.
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reg s_wr_done;
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reg s_wr_done;
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reg s_rd_done;
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reg s_rd_done;
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reg [6:0] s_wr_addr = 7'd0;
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reg [6:0] s_wr_addr = 7'd0;
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reg [31:0] s_wr_data = 32'd0;
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reg [31:0] s_wr_data = 32'd0;
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reg [3:0] s_wr_vld = 4'b0000;
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reg [3:0] s_wr_vld = 4'b0000;
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reg s_wr_go = 1'b0;
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reg s_wr_go = 1'b0;
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reg [6:0] s_rd_addr = 7'd0;
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reg [6:0] s_rd_addr = 7'd0;
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reg s_rd_go = 1'b0;
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reg s_rd_go = 1'b0;
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initial begin
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initial begin
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// 1-byte write
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// 1-byte write
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repeat (1500) @ (posedge s_aclk);
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repeat (1500) @ (posedge s_aclk);
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s_wr_addr <= 7'h03;
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s_wr_addr <= 7'h03;
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s_wr_data <= 32'h03020100;
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s_wr_data <= 32'h03020100;
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s_wr_vld <= 4'b1000;
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s_wr_vld <= 4'b1000;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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// 2-byte write
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// 2-byte write
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_wr_addr <= 7'h06;
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s_wr_addr <= 7'h06;
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s_wr_data <= 32'h07060504;
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s_wr_data <= 32'h07060504;
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s_wr_vld <= 4'b1100;
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s_wr_vld <= 4'b1100;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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// 2-byte write
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// 2-byte write
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_wr_addr <= 7'h08;
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s_wr_addr <= 7'h08;
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s_wr_data <= 32'h0B0A0908;
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s_wr_data <= 32'h0B0A0908;
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s_wr_vld <= 4'b0011;
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s_wr_vld <= 4'b0011;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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// 4-byte write
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// 4-byte write
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_wr_addr <= 7'h0C;
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s_wr_addr <= 7'h0C;
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s_wr_data <= 32'h0F0E0D0C;
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s_wr_data <= 32'h0F0E0D0C;
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s_wr_vld <= 4'b0011;
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s_wr_vld <= 4'b0011;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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// isolated read
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// isolated read
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_rd_addr <= 7'd16;
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s_rd_addr <= 7'd16;
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s_rd_go <= 1'b1; @ (posedge s_aclk); s_rd_go <= 1'b0; wait(s_rd_done); @ (posedge s_aclk);
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s_rd_go <= 1'b1; @ (posedge s_aclk); s_rd_go <= 1'b0; wait(s_rd_done); @ (posedge s_aclk);
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// simultaneous read and write
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// simultaneous read and write
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_wr_addr <= 7'h10;
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s_wr_addr <= 7'h10;
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s_wr_data <= 32'h13121110;
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s_wr_data <= 32'h13121110;
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s_wr_vld <= 4'b1111;
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s_wr_vld <= 4'b1111;
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s_rd_addr <= 7'd04;
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s_rd_addr <= 7'd04;
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s_wr_go <= 1'b1; s_rd_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; s_rd_go <= 1'b0; wait(s_wr_done); wait(s_rd_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; s_rd_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; s_rd_go <= 1'b0; wait(s_wr_done); wait(s_rd_done); @ (posedge s_aclk);
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// read preceding write by 1 clock cycle
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// read preceding write by 1 clock cycle
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_rd_addr <= 7'd08;
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s_rd_addr <= 7'd08;
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s_wr_addr <= 7'h14;
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s_wr_addr <= 7'h14;
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s_wr_data <= 32'h17161514;
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s_wr_data <= 32'h17161514;
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s_wr_vld <= 4'b1111;
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s_wr_vld <= 4'b1111;
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s_rd_go <= 1'b1; @ (posedge s_aclk); s_rd_go <= 1'b0;
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s_rd_go <= 1'b1; @ (posedge s_aclk); s_rd_go <= 1'b0;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0;
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wait(s_rd_done); wait(s_wr_done); @ (posedge s_aclk);
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wait(s_rd_done); wait(s_wr_done); @ (posedge s_aclk);
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// signal termination to the micro controller by writing a 4 to the byte at address 16;
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// signal termination to the micro controller by writing a 4 to the byte at address 16;
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repeat (100) @ (posedge s_aclk);
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repeat (100) @ (posedge s_aclk);
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s_wr_addr <= 7'h10;
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s_wr_addr <= 7'h10;
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s_wr_data <= 32'h04;
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s_wr_data <= 32'h04;
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s_wr_vld <= 4'b0001;
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s_wr_vld <= 4'b0001;
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s_rd_addr <= 7'd0;
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s_rd_addr <= 7'd0;
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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s_wr_go <= 1'b1; @ (posedge s_aclk); s_wr_go <= 1'b0; wait(s_wr_done); @ (posedge s_aclk);
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end
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end
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// Initiate writes and indicate their termination.
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// Initiate writes and indicate their termination.
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initial s_wr_done = 1'b0;
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initial s_wr_done = 1'b0;
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reg [2:0] s_wr_acks = 3'b000;
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reg [2:0] s_wr_acks = 3'b000;
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reg s_awvalid = 1'b0;
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reg s_awvalid = 1'b0;
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reg s_wvalid = 1'b0;
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reg s_wvalid = 1'b0;
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reg s_bready = 1'b0;
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reg s_bready = 1'b0;
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wire s_awready;
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wire s_awready;
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wire s_wready;
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wire s_wready;
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wire s_bvalid;
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wire s_bvalid;
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always @ (posedge s_aclk) begin
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always @ (posedge s_aclk) begin
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s_wr_done <= 1'b0;
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s_wr_done <= 1'b0;
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s_wr_acks <= s_wr_acks;
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s_wr_acks <= s_wr_acks;
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s_bready <= 1'b0;
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s_bready <= 1'b0;
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if (s_wr_acks == 3'b111) begin
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if (s_wr_acks == 3'b111) begin
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s_wr_done <= 1'b1;
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s_wr_done <= 1'b1;
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s_wr_acks <= 3'b000;
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s_wr_acks <= 3'b000;
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end
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end
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if (s_wr_go) begin
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if (s_wr_go) begin
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s_awvalid <= 1'b1;
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s_awvalid <= 1'b1;
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s_wvalid <= 1'b1;
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s_wvalid <= 1'b1;
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end
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end
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if (s_awvalid && s_awready) begin
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if (s_awvalid && s_awready) begin
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s_awvalid <= 1'b0;
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s_awvalid <= 1'b0;
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s_wr_acks[0] <= 1'b1;
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s_wr_acks[0] <= 1'b1;
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end
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end
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if (s_wvalid && s_wready) begin
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if (s_wvalid && s_wready) begin
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s_wvalid <= 1'b0;
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s_wvalid <= 1'b0;
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s_wr_acks[1] <= 1'b1;
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s_wr_acks[1] <= 1'b1;
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end
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end
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if (s_bvalid && ~s_bready && ~s_wr_acks[2])
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if (s_bvalid && ~s_bready && ~s_wr_acks[2])
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s_bready <= 1'b1;
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s_bready <= 1'b1;
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if (s_bvalid && s_bready)
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if (s_bvalid && s_bready)
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s_wr_acks[2] <= 1'b1;
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s_wr_acks[2] <= 1'b1;
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end
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end
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// Initiate reads and indicate their termination
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// Initiate reads and indicate their termination
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localparam S_INIT_RREADY = 1'b1; // observed Xilinx behavior -- always high
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initial s_rd_done = 1'b0;
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initial s_rd_done = 1'b0;
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reg [1:0] s_rd_acks = 2'b00;
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reg [1:0] s_rd_acks = 2'b00;
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reg s_arvalid = 1'b0;
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reg s_arvalid = 1'b0;
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reg s_rready = 1'b0;
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reg s_rready = 1'b0;
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wire s_arready;
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wire s_arready;
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wire s_rvalid;
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wire s_rvalid;
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always @ (posedge s_aclk) begin
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always @ (posedge s_aclk) begin
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s_rd_done <= 1'b0;
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s_rd_done <= 1'b0;
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s_rd_acks <= s_rd_acks;
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s_rd_acks <= s_rd_acks;
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s_rready <= 1'b0;
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s_rready <= S_INIT_RREADY;
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if (s_rd_acks == 2'b11) begin
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if (s_rd_acks == 2'b11) begin
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s_rd_done <= 1'b1;
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s_rd_done <= 1'b1;
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s_rd_acks <= 2'b00;
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s_rd_acks <= 2'b00;
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end
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end
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if (s_rd_go)
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if (s_rd_go)
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s_arvalid <= 1'b1;
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s_arvalid <= 1'b1;
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if (s_arvalid && s_arready) begin
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if (s_arvalid && s_arready) begin
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s_arvalid <= 1'b0;
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s_arvalid <= 1'b0;
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s_rd_acks[0] <= 1'b1;
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s_rd_acks[0] <= 1'b1;
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end
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end
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if (s_rvalid && ~s_rready && ~s_rd_acks[1])
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if (s_rvalid && ~s_rready && ~s_rd_acks[1])
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s_rready <= 1'b1;
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s_rready <= 1'b1;
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if (s_rvalid && s_rready)
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if (s_rvalid && s_rready)
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s_rd_acks[1] <= 1'b1;
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s_rd_acks[1] <= 1'b1;
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end
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end
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//
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//
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// Instantiate the micro controller, its data output, and program termination.
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// Instantiate the micro controller, its data output, and program termination.
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//
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//
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wire [1:0] s_bresp;
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wire [1:0] s_bresp;
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wire [31:0] s_rdata;
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wire [31:0] s_rdata;
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wire [1:0] s_rresp;
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wire [1:0] s_rresp;
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wire [7:0] s_addr;
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wire [7:0] s_addr;
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wire [7:0] s_data;
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wire [7:0] s_data;
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wire s_data_wr;
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wire s_data_wr;
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wire s_done;
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wire s_done;
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tb_AXI4_Lite_Slave_DualPortRAM uut(
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tb_AXI4_Lite_Slave_DualPortRAM uut(
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// synchronous reset and processor clock
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// synchronous reset and processor clock
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.i_rst (s_rst),
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.i_rst (s_rst),
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.i_clk (s_clk),
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.i_clk (s_clk),
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// AXI4-Lite Slave I/F
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// AXI4-Lite Slave I/F
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.i_axi_lite_aresetn (1'b1),
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.i_axi_lite_aresetn (1'b1),
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.i_axi_lite_aclk (s_aclk),
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.i_axi_lite_aclk (s_aclk),
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.i_axi_lite_awvalid (s_awvalid),
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.i_axi_lite_awvalid (s_awvalid),
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.o_axi_lite_awready (s_awready),
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.o_axi_lite_awready (s_awready),
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.i_axi_lite_awaddr (s_wr_addr),
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.i_axi_lite_awaddr (s_wr_addr),
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.i_axi_lite_wvalid (s_wvalid),
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.i_axi_lite_wvalid (s_wvalid),
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.o_axi_lite_wready (s_wready),
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.o_axi_lite_wready (s_wready),
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.i_axi_lite_wdata (s_wr_data),
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.i_axi_lite_wdata (s_wr_data),
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.i_axi_lite_wstrb (s_wr_vld),
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.i_axi_lite_wstrb (s_wr_vld),
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.o_axi_lite_bresp (s_bresp),
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.o_axi_lite_bresp (s_bresp),
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.o_axi_lite_bvalid (s_bvalid),
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.o_axi_lite_bvalid (s_bvalid),
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.i_axi_lite_bready (s_bready),
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.i_axi_lite_bready (s_bready),
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.i_axi_lite_arvalid (s_arvalid),
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.i_axi_lite_arvalid (s_arvalid),
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.o_axi_lite_arready (s_arready),
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.o_axi_lite_arready (s_arready),
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.i_axi_lite_araddr (7'd0),
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.i_axi_lite_araddr (7'd0),
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.o_axi_lite_rvalid (s_rvalid),
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.o_axi_lite_rvalid (s_rvalid),
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.i_axi_lite_rready (s_rready),
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.i_axi_lite_rready (s_rready),
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.o_axi_lite_rdata (s_rdata),
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.o_axi_lite_rdata (s_rdata),
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.o_axi_lite_rresp (s_rresp),
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.o_axi_lite_rresp (s_rresp),
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// diagnostic output
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// diagnostic output
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.o_diag_addr (s_addr),
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.o_diag_addr (s_addr),
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.o_diag_data (s_data),
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.o_diag_data (s_data),
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.o_diag_wr (s_data_wr),
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.o_diag_wr (s_data_wr),
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// program termination
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// program termination
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.o_done (s_done)
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.o_done (s_done)
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);
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);
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always @ (posedge s_clk)
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always @ (posedge s_clk)
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if (s_data_wr)
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if (s_data_wr)
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$display("%12d : %h %h", $time, s_addr, s_data);
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$display("%12d : %h %h", $time, s_addr, s_data);
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always @ (posedge s_clk)
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always @ (posedge s_clk)
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if (s_done)
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if (s_done)
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$finish;
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$finish;
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//initial begin
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// $dumpfile("tb.vcd");
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// $dumpvars();
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//end
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endmodule
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endmodule
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