OpenCores
URL https://opencores.org/ocsvn/ssbcc/ssbcc/trunk

Subversion Repositories ssbcc

[/] [ssbcc/] [trunk/] [lib/] [9x8/] [tb/] [cmp_8bit_uu/] [uc.9x8] - Diff between revs 2 and 4

Only display areas with differences | Details | Blame | View Log

Rev 2 Rev 4
# Copyright 2013, Sinclair R.F., Inc.
# Copyright 2013, Sinclair R.F., Inc.
# Test bench for the math libraries.
# Test bench for the icomparison math library.
 
 
ARCHITECTURE core/9x8 Verilog
ARCHITECTURE core/9x8 Verilog
INSTRUCTION     1024
INSTRUCTION     1024
DATA_STACK      32
DATA_STACK      32
RETURN_STACK    32
RETURN_STACK    32
PORTCOMMENT 8-bit test values
PORTCOMMENT 8-bit test values
OUTPORT 8-bit,strobe   o_value,o_value_wr O_VALUE
OUTPORT 8-bit,strobe   o_value,o_value_wr O_VALUE
PORTCOMMENT termination strobe
PORTCOMMENT termination strobe
OUTPORT strobe  o_terminate_str O_TERMINATE
OUTPORT strobe  o_terminate_str O_TERMINATE
ASSEMBLY uc.s
ASSEMBLY uc.s
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.