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//////////////////////////////////////////////////////////////////////
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//// statled.v ////
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//// ////
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//// This file is part of the Status LED module. ////
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//// http://www.opencores.org/projects/statled/ ////
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//// ////
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//// Author: ////
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//// -Dimitar Dimitrov, d.dimitrov@bitlocker.eu ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`timescale 1ns / 100ps
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`timescale 1ns / 100ps
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/******************************************************************************
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* Status LED module
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*
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* Use single LED ouput to displays various internal states as blink codes.
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* http://www.opencores.org/cores/statled
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*
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******************************************************************************/
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module statled (
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module statled (
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input clk,
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input clk,
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input rst,
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input rst,
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input [3:0] status,
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input [3:0] status,
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output led
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output led
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);
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);
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`include "statled_par.v"
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`include "statled_par.v"
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reg [32:0] pre; // Prescaler
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reg [32:0] pre; // Prescaler
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reg [7:0] bcnt; // Bit counter
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reg [7:0] bcnt; // Bit counter
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reg [15:0] lsr; // LED shift register
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reg [15:0] lsr; // LED shift register
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reg [15:0] cr; // Code register
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reg [15:0] cr; // Code register
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reg [3:0] str; // Status register
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reg [3:0] str; // Status register
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wire rate; // LED rate
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wire rate; // LED rate
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//-----------------------------------------------------------------------------
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//--------------------------------------------------------------------
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// LED rate
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// LED rate
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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pre <= #tDLY 0;
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pre <= #tDLY 0;
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else if (rate)
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else if (rate)
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pre <= #tDLY 0;
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pre <= #tDLY 0;
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else
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else
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pre <= #tDLY pre + 1;
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pre <= #tDLY pre + 1;
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assign rate = (pre == STATLED_PULSE_CLKCNT);
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assign rate = (pre == STATLED_PULSE_CLKCNT);
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//-----------------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Capture status inputs
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// Capture status inputs
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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str <= #tDLY 0;
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str <= #tDLY 0;
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else
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else
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str <= #tDLY status;
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str <= #tDLY status;
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//-----------------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Shift register and bit counter
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// Shift register and bit counter
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//
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//
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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bcnt <= #tDLY 15;
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bcnt <= #tDLY 15;
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else if (bcnt == 16)
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else if (bcnt == 16)
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bcnt <= #tDLY 0;
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bcnt <= #tDLY 0;
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else if (rate)
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else if (rate)
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bcnt <= #tDLY bcnt + 1;
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bcnt <= #tDLY bcnt + 1;
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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lsr <= #tDLY 0;
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lsr <= #tDLY 0;
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else if (bcnt == 16)
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else if (bcnt == 16)
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lsr <= #tDLY cr;
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lsr <= #tDLY cr;
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else if (rate)
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else if (rate)
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lsr <= #tDLY lsr << 1;
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lsr <= #tDLY lsr << 1;
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assign led = rst? 1 : lsr[15];
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assign led = rst? 1 : lsr[15];
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//-----------------------------------------------------------------------------
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//--------------------------------------------------------------------
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// Codes
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// Codes
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//
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//
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always @*
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always @*
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case(str)
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case(str)
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0: cr = CODE_50_50; // Default code
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0: cr = CODE_50_50; // Default code
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1: cr = CODE_ONE; // State 1
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1: cr = CODE_ONE; // State 1
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2: cr = CODE_TWO; // State 2
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2: cr = CODE_TWO; // State 2
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3: cr = CODE_THREE; // ....
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3: cr = CODE_THREE; // ....
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4: cr = CODE_FOUR; //
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4: cr = CODE_FOUR; //
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5: cr = CODE_FIVE; //
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5: cr = CODE_FIVE; //
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6: cr = CODE_SIX; //
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6: cr = CODE_SIX; //
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default: cr = 0;
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default: cr = 0;
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endcase
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endcase
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endmodule
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endmodule
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