-- VHDL structural description generated from `sm16plus1mul`
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-- VHDL structural description generated from `sm16plus1mul`
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-- date : Sat Sep 8 04:28:34 2001
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-- date : Sat Sep 8 04:28:34 2001
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-- Entity Declaration
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-- Entity Declaration
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ENTITY sm16plus1mul IS
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ENTITY sm16plus1mul IS
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PORT (
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PORT (
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in1 : in BIT_VECTOR (0 TO 15); -- in1
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in1 : in BIT_VECTOR (0 TO 15); -- in1
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in2 : in BIT_VECTOR (0 TO 15); -- in2
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in2 : in BIT_VECTOR (0 TO 15); -- in2
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en : in BIT; -- en
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en : in BIT; -- en
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clr : in BIT; -- clr
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clr : in BIT; -- clr
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mulout : out BIT_VECTOR (0 TO 15); -- mulout
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mulout : out BIT_VECTOR (0 TO 15); -- mulout
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END sm16plus1mul;
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END sm16plus1mul;
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-- Architecture Declaration
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-- Architecture Declaration
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ARCHITECTURE VST OF sm16plus1mul IS
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ARCHITECTURE VST OF sm16plus1mul IS
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COMPONENT comp1_glopg
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COMPONENT comp1_glopg
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port (
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port (
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kin : in BIT_VECTOR(15 DOWNTO 0); -- kin
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kin : in BIT_VECTOR(15 DOWNTO 0); -- kin
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kout1 : out BIT_VECTOR(16 DOWNTO 0); -- kout1
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kout1 : out BIT_VECTOR(16 DOWNTO 0); -- kout1
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT mul17_glopg
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COMPONENT mul17_glopg
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port (
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port (
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a : in BIT_VECTOR(16 DOWNTO 0); -- a
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a : in BIT_VECTOR(16 DOWNTO 0); -- a
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b : in BIT_VECTOR(16 DOWNTO 0); -- b
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b : in BIT_VECTOR(16 DOWNTO 0); -- b
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sum : out BIT_VECTOR(31 DOWNTO 0); -- sum
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sum : out BIT_VECTOR(31 DOWNTO 0); -- sum
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT comp2_glopg
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COMPONENT comp2_glopg
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port (
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port (
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vss : in BIT; -- vss
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vss : in BIT; -- vss
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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kout2 : out BIT_VECTOR(0 TO 15); -- kout2
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kout2 : out BIT_VECTOR(0 TO 15); -- kout2
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q : in BIT_VECTOR(0 TO 15); -- q
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q : in BIT_VECTOR(0 TO 15); -- q
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p : in BIT_VECTOR(0 TO 15) -- p
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p : in BIT_VECTOR(0 TO 15) -- p
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT subtract16_glopg
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COMPONENT subtract16_glopg
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port (
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port (
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a : in BIT_VECTOR(0 TO 15); -- a
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a : in BIT_VECTOR(0 TO 15); -- a
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b : in BIT_VECTOR(0 TO 15); -- b
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b : in BIT_VECTOR(0 TO 15); -- b
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s : out BIT_VECTOR(0 TO 15); -- s
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s : out BIT_VECTOR(0 TO 15); -- s
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT reg16_glopf
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COMPONENT reg16_glopf
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port (
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port (
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d : in BIT_VECTOR(0 TO 15); -- d
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d : in BIT_VECTOR(0 TO 15); -- d
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en : in BIT; -- en
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en : in BIT; -- en
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clr : in BIT; -- clr
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clr : in BIT; -- clr
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q : inout BIT_VECTOR(0 TO 15); -- q
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q : inout BIT_VECTOR(0 TO 15); -- q
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT m16adder_glopg
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COMPONENT m16adder_glopg
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port (
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port (
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a : in BIT_VECTOR(0 TO 15); -- a
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a : in BIT_VECTOR(0 TO 15); -- a
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b : in BIT_VECTOR(0 TO 15); -- b
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b : in BIT_VECTOR(0 TO 15); -- b
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s : out BIT_VECTOR(0 TO 15); -- s
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s : out BIT_VECTOR(0 TO 15); -- s
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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SIGNAL dif_0 : BIT; -- dif 0
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SIGNAL dif_0 : BIT; -- dif 0
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SIGNAL dif_1 : BIT; -- dif 1
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SIGNAL dif_1 : BIT; -- dif 1
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SIGNAL dif_2 : BIT; -- dif 2
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SIGNAL dif_2 : BIT; -- dif 2
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SIGNAL dif_3 : BIT; -- dif 3
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SIGNAL dif_3 : BIT; -- dif 3
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SIGNAL dif_4 : BIT; -- dif 4
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SIGNAL dif_4 : BIT; -- dif 4
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SIGNAL dif_5 : BIT; -- dif 5
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SIGNAL dif_5 : BIT; -- dif 5
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SIGNAL dif_6 : BIT; -- dif 6
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SIGNAL dif_6 : BIT; -- dif 6
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SIGNAL dif_7 : BIT; -- dif 7
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SIGNAL dif_7 : BIT; -- dif 7
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SIGNAL dif_8 : BIT; -- dif 8
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SIGNAL dif_8 : BIT; -- dif 8
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SIGNAL dif_9 : BIT; -- dif 9
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SIGNAL dif_9 : BIT; -- dif 9
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SIGNAL dif_10 : BIT; -- dif 10
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SIGNAL dif_10 : BIT; -- dif 10
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SIGNAL dif_11 : BIT; -- dif 11
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SIGNAL dif_11 : BIT; -- dif 11
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SIGNAL dif_12 : BIT; -- dif 12
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SIGNAL dif_12 : BIT; -- dif 12
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SIGNAL dif_13 : BIT; -- dif 13
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SIGNAL dif_13 : BIT; -- dif 13
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SIGNAL dif_14 : BIT; -- dif 14
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SIGNAL dif_14 : BIT; -- dif 14
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SIGNAL dif_15 : BIT; -- dif 15
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SIGNAL dif_15 : BIT; -- dif 15
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SIGNAL kout1a_0 : BIT; -- kout1a 0
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SIGNAL kout1a_0 : BIT; -- kout1a 0
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SIGNAL kout1a_1 : BIT; -- kout1a 1
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SIGNAL kout1a_1 : BIT; -- kout1a 1
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SIGNAL kout1a_2 : BIT; -- kout1a 2
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SIGNAL kout1a_2 : BIT; -- kout1a 2
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SIGNAL kout1a_3 : BIT; -- kout1a 3
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SIGNAL kout1a_3 : BIT; -- kout1a 3
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SIGNAL kout1a_4 : BIT; -- kout1a 4
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SIGNAL kout1a_4 : BIT; -- kout1a 4
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SIGNAL kout1a_5 : BIT; -- kout1a 5
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SIGNAL kout1a_5 : BIT; -- kout1a 5
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SIGNAL kout1a_6 : BIT; -- kout1a 6
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SIGNAL kout1a_6 : BIT; -- kout1a 6
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SIGNAL kout1a_7 : BIT; -- kout1a 7
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SIGNAL kout1a_7 : BIT; -- kout1a 7
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SIGNAL kout1a_8 : BIT; -- kout1a 8
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SIGNAL kout1a_8 : BIT; -- kout1a 8
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SIGNAL kout1a_9 : BIT; -- kout1a 9
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SIGNAL kout1a_9 : BIT; -- kout1a 9
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SIGNAL kout1a_10 : BIT; -- kout1a 10
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SIGNAL kout1a_10 : BIT; -- kout1a 10
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SIGNAL kout1a_11 : BIT; -- kout1a 11
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SIGNAL kout1a_11 : BIT; -- kout1a 11
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SIGNAL kout1a_12 : BIT; -- kout1a 12
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SIGNAL kout1a_12 : BIT; -- kout1a 12
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SIGNAL kout1a_13 : BIT; -- kout1a 13
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SIGNAL kout1a_13 : BIT; -- kout1a 13
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SIGNAL kout1a_14 : BIT; -- kout1a 14
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SIGNAL kout1a_14 : BIT; -- kout1a 14
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SIGNAL kout1a_15 : BIT; -- kout1a 15
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SIGNAL kout1a_15 : BIT; -- kout1a 15
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SIGNAL kout1a_16 : BIT; -- kout1a 16
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SIGNAL kout1a_16 : BIT; -- kout1a 16
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SIGNAL kout1b_0 : BIT; -- kout1b 0
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SIGNAL kout1b_0 : BIT; -- kout1b 0
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SIGNAL kout1b_1 : BIT; -- kout1b 1
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SIGNAL kout1b_1 : BIT; -- kout1b 1
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SIGNAL kout1b_2 : BIT; -- kout1b 2
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SIGNAL kout1b_2 : BIT; -- kout1b 2
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SIGNAL kout1b_3 : BIT; -- kout1b 3
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SIGNAL kout1b_3 : BIT; -- kout1b 3
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SIGNAL kout1b_4 : BIT; -- kout1b 4
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SIGNAL kout1b_4 : BIT; -- kout1b 4
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SIGNAL kout1b_5 : BIT; -- kout1b 5
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SIGNAL kout1b_5 : BIT; -- kout1b 5
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SIGNAL kout1b_6 : BIT; -- kout1b 6
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SIGNAL kout1b_6 : BIT; -- kout1b 6
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SIGNAL kout1b_7 : BIT; -- kout1b 7
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SIGNAL kout1b_7 : BIT; -- kout1b 7
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SIGNAL kout1b_8 : BIT; -- kout1b 8
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SIGNAL kout1b_8 : BIT; -- kout1b 8
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SIGNAL kout1b_9 : BIT; -- kout1b 9
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SIGNAL kout1b_9 : BIT; -- kout1b 9
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SIGNAL kout1b_10 : BIT; -- kout1b 10
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SIGNAL kout1b_10 : BIT; -- kout1b 10
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SIGNAL kout1b_11 : BIT; -- kout1b 11
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SIGNAL kout1b_11 : BIT; -- kout1b 11
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SIGNAL kout1b_12 : BIT; -- kout1b 12
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SIGNAL kout1b_12 : BIT; -- kout1b 12
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SIGNAL kout1b_13 : BIT; -- kout1b 13
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SIGNAL kout1b_13 : BIT; -- kout1b 13
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SIGNAL kout1b_14 : BIT; -- kout1b 14
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SIGNAL kout1b_14 : BIT; -- kout1b 14
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SIGNAL kout1b_15 : BIT; -- kout1b 15
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SIGNAL kout1b_15 : BIT; -- kout1b 15
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SIGNAL kout1b_16 : BIT; -- kout1b 16
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SIGNAL kout1b_16 : BIT; -- kout1b 16
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SIGNAL kout2_0 : BIT; -- kout2 0
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SIGNAL kout2_0 : BIT; -- kout2 0
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SIGNAL kout2_1 : BIT; -- kout2 1
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SIGNAL kout2_1 : BIT; -- kout2 1
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SIGNAL kout2_2 : BIT; -- kout2 2
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SIGNAL kout2_2 : BIT; -- kout2 2
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SIGNAL kout2_3 : BIT; -- kout2 3
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SIGNAL kout2_3 : BIT; -- kout2 3
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SIGNAL kout2_4 : BIT; -- kout2 4
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SIGNAL kout2_4 : BIT; -- kout2 4
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SIGNAL kout2_5 : BIT; -- kout2 5
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SIGNAL kout2_5 : BIT; -- kout2 5
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SIGNAL kout2_6 : BIT; -- kout2 6
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SIGNAL kout2_6 : BIT; -- kout2 6
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SIGNAL kout2_7 : BIT; -- kout2 7
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SIGNAL kout2_7 : BIT; -- kout2 7
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SIGNAL kout2_8 : BIT; -- kout2 8
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SIGNAL kout2_8 : BIT; -- kout2 8
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SIGNAL kout2_9 : BIT; -- kout2 9
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SIGNAL kout2_9 : BIT; -- kout2 9
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SIGNAL kout2_10 : BIT; -- kout2 10
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SIGNAL kout2_10 : BIT; -- kout2 10
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SIGNAL kout2_11 : BIT; -- kout2 11
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SIGNAL kout2_11 : BIT; -- kout2 11
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SIGNAL kout2_12 : BIT; -- kout2 12
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SIGNAL kout2_12 : BIT; -- kout2 12
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SIGNAL kout2_13 : BIT; -- kout2 13
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SIGNAL kout2_13 : BIT; -- kout2 13
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SIGNAL kout2_14 : BIT; -- kout2 14
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SIGNAL kout2_14 : BIT; -- kout2 14
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SIGNAL kout2_15 : BIT; -- kout2 15
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SIGNAL kout2_15 : BIT; -- kout2 15
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SIGNAL r1_0 : BIT; -- r1 0
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SIGNAL r1_0 : BIT; -- r1 0
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SIGNAL r1_1 : BIT; -- r1 1
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SIGNAL r1_1 : BIT; -- r1 1
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SIGNAL r1_2 : BIT; -- r1 2
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SIGNAL r1_2 : BIT; -- r1 2
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SIGNAL r1_3 : BIT; -- r1 3
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SIGNAL r1_3 : BIT; -- r1 3
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SIGNAL r1_4 : BIT; -- r1 4
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SIGNAL r1_4 : BIT; -- r1 4
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SIGNAL r1_5 : BIT; -- r1 5
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SIGNAL r1_5 : BIT; -- r1 5
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SIGNAL r1_6 : BIT; -- r1 6
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SIGNAL r1_6 : BIT; -- r1 6
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SIGNAL r1_7 : BIT; -- r1 7
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SIGNAL r1_7 : BIT; -- r1 7
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SIGNAL r1_8 : BIT; -- r1 8
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SIGNAL r1_8 : BIT; -- r1 8
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SIGNAL r1_9 : BIT; -- r1 9
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SIGNAL r1_9 : BIT; -- r1 9
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SIGNAL r1_10 : BIT; -- r1 10
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SIGNAL r1_10 : BIT; -- r1 10
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SIGNAL r1_11 : BIT; -- r1 11
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SIGNAL r1_11 : BIT; -- r1 11
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SIGNAL r1_12 : BIT; -- r1 12
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SIGNAL r1_12 : BIT; -- r1 12
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SIGNAL r1_13 : BIT; -- r1 13
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SIGNAL r1_13 : BIT; -- r1 13
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SIGNAL r1_14 : BIT; -- r1 14
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SIGNAL r1_14 : BIT; -- r1 14
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SIGNAL r1_15 : BIT; -- r1 15
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SIGNAL r1_15 : BIT; -- r1 15
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SIGNAL r2_0 : BIT; -- r2 0
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SIGNAL r2_0 : BIT; -- r2 0
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SIGNAL r2_1 : BIT; -- r2 1
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SIGNAL r2_1 : BIT; -- r2 1
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SIGNAL r2_2 : BIT; -- r2 2
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SIGNAL r2_2 : BIT; -- r2 2
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SIGNAL r2_3 : BIT; -- r2 3
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SIGNAL r2_3 : BIT; -- r2 3
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SIGNAL r2_4 : BIT; -- r2 4
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SIGNAL r2_4 : BIT; -- r2 4
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SIGNAL r2_5 : BIT; -- r2 5
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SIGNAL r2_5 : BIT; -- r2 5
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SIGNAL r2_6 : BIT; -- r2 6
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SIGNAL r2_6 : BIT; -- r2 6
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SIGNAL r2_7 : BIT; -- r2 7
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SIGNAL r2_7 : BIT; -- r2 7
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SIGNAL r2_8 : BIT; -- r2 8
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SIGNAL r2_8 : BIT; -- r2 8
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SIGNAL r2_9 : BIT; -- r2 9
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SIGNAL r2_9 : BIT; -- r2 9
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SIGNAL r2_10 : BIT; -- r2 10
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SIGNAL r2_10 : BIT; -- r2 10
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SIGNAL r2_11 : BIT; -- r2 11
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SIGNAL r2_11 : BIT; -- r2 11
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SIGNAL r2_12 : BIT; -- r2 12
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SIGNAL r2_12 : BIT; -- r2 12
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SIGNAL r2_13 : BIT; -- r2 13
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SIGNAL r2_13 : BIT; -- r2 13
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SIGNAL r2_14 : BIT; -- r2 14
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SIGNAL r2_14 : BIT; -- r2 14
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SIGNAL r2_15 : BIT; -- r2 15
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SIGNAL r2_15 : BIT; -- r2 15
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SIGNAL res_0 : BIT; -- res 0
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SIGNAL res_0 : BIT; -- res 0
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SIGNAL res_1 : BIT; -- res 1
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SIGNAL res_1 : BIT; -- res 1
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SIGNAL res_2 : BIT; -- res 2
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SIGNAL res_2 : BIT; -- res 2
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SIGNAL res_3 : BIT; -- res 3
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SIGNAL res_3 : BIT; -- res 3
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SIGNAL res_4 : BIT; -- res 4
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SIGNAL res_4 : BIT; -- res 4
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SIGNAL res_5 : BIT; -- res 5
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SIGNAL res_5 : BIT; -- res 5
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SIGNAL res_6 : BIT; -- res 6
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SIGNAL res_6 : BIT; -- res 6
|
SIGNAL res_7 : BIT; -- res 7
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SIGNAL res_7 : BIT; -- res 7
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SIGNAL res_8 : BIT; -- res 8
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SIGNAL res_8 : BIT; -- res 8
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SIGNAL res_9 : BIT; -- res 9
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SIGNAL res_9 : BIT; -- res 9
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SIGNAL res_10 : BIT; -- res 10
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SIGNAL res_10 : BIT; -- res 10
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SIGNAL res_11 : BIT; -- res 11
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SIGNAL res_11 : BIT; -- res 11
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SIGNAL res_12 : BIT; -- res 12
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SIGNAL res_12 : BIT; -- res 12
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SIGNAL res_13 : BIT; -- res 13
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SIGNAL res_13 : BIT; -- res 13
|
SIGNAL res_14 : BIT; -- res 14
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SIGNAL res_14 : BIT; -- res 14
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SIGNAL res_15 : BIT; -- res 15
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SIGNAL res_15 : BIT; -- res 15
|
SIGNAL res_16 : BIT; -- res 16
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SIGNAL res_16 : BIT; -- res 16
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SIGNAL res_17 : BIT; -- res 17
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SIGNAL res_17 : BIT; -- res 17
|
SIGNAL res_18 : BIT; -- res 18
|
SIGNAL res_18 : BIT; -- res 18
|
SIGNAL res_19 : BIT; -- res 19
|
SIGNAL res_19 : BIT; -- res 19
|
SIGNAL res_20 : BIT; -- res 20
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SIGNAL res_20 : BIT; -- res 20
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SIGNAL res_21 : BIT; -- res 21
|
SIGNAL res_21 : BIT; -- res 21
|
SIGNAL res_22 : BIT; -- res 22
|
SIGNAL res_22 : BIT; -- res 22
|
SIGNAL res_23 : BIT; -- res 23
|
SIGNAL res_23 : BIT; -- res 23
|
SIGNAL res_24 : BIT; -- res 24
|
SIGNAL res_24 : BIT; -- res 24
|
SIGNAL res_25 : BIT; -- res 25
|
SIGNAL res_25 : BIT; -- res 25
|
SIGNAL res_26 : BIT; -- res 26
|
SIGNAL res_26 : BIT; -- res 26
|
SIGNAL res_27 : BIT; -- res 27
|
SIGNAL res_27 : BIT; -- res 27
|
SIGNAL res_28 : BIT; -- res 28
|
SIGNAL res_28 : BIT; -- res 28
|
SIGNAL res_29 : BIT; -- res 29
|
SIGNAL res_29 : BIT; -- res 29
|
SIGNAL res_30 : BIT; -- res 30
|
SIGNAL res_30 : BIT; -- res 30
|
SIGNAL res_31 : BIT; -- res 31
|
SIGNAL res_31 : BIT; -- res 31
|
|
|
BEGIN
|
BEGIN
|
|
|
com1a : comp1_glopg
|
com1a : comp1_glopg
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
kout1 => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0,
|
kout1 => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0,
|
kin => in1(15)& in1(14)& in1(13)& in1(12)& in1(11)& in1(10)& in1(9)& in1(8)& in1(7)& in1(6)& in1(5)& in1(4)& in1(3)& in1(2)& in1(1)& in1(0));
|
kin => in1(15)& in1(14)& in1(13)& in1(12)& in1(11)& in1(10)& in1(9)& in1(8)& in1(7)& in1(6)& in1(5)& in1(4)& in1(3)& in1(2)& in1(1)& in1(0));
|
com1b : comp1_glopg
|
com1b : comp1_glopg
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
kout1 => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
|
kout1 => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
|
kin => in2(15)& in2(14)& in2(13)& in2(12)& in2(11)& in2(10)& in2(9)& in2(8)& in2(7)& in2(6)& in2(5)& in2(4)& in2(3)& in2(2)& in2(1)& in2(0));
|
kin => in2(15)& in2(14)& in2(13)& in2(12)& in2(11)& in2(10)& in2(9)& in2(8)& in2(7)& in2(6)& in2(5)& in2(4)& in2(3)& in2(2)& in2(1)& in2(0));
|
mul : mul17_glopg
|
mul : mul17_glopg
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
sum => res_31& res_30& res_29& res_28& res_27& res_26& res_25& res_24& res_23& res_22& res_21& res_20& res_19& res_18& res_17& res_16& res_15& res_14& res_13& res_12& res_11& res_10& res_9& res_8& res_7& res_6& res_5& res_4& res_3& res_2& res_1& res_0,
|
sum => res_31& res_30& res_29& res_28& res_27& res_26& res_25& res_24& res_23& res_22& res_21& res_20& res_19& res_18& res_17& res_16& res_15& res_14& res_13& res_12& res_11& res_10& res_9& res_8& res_7& res_6& res_5& res_4& res_3& res_2& res_1& res_0,
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b => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
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b => kout1b_16& kout1b_15& kout1b_14& kout1b_13& kout1b_12& kout1b_11& kout1b_10& kout1b_9& kout1b_8& kout1b_7& kout1b_6& kout1b_5& kout1b_4& kout1b_3& kout1b_2& kout1b_1& kout1b_0,
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a => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0);
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a => kout1a_16& kout1a_15& kout1a_14& kout1a_13& kout1a_12& kout1a_11& kout1a_10& kout1a_9& kout1a_8& kout1a_7& kout1a_6& kout1a_5& kout1a_4& kout1a_3& kout1a_2& kout1a_1& kout1a_0);
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com2 : comp2_glopg
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com2 : comp2_glopg
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PORT MAP (
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PORT MAP (
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p => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15,
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p => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15,
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q => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
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q => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
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kout2 => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15,
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kout2 => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15,
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vdd => vdd,
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vdd => vdd,
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vss => vss);
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vss => vss);
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sub : subtract16_glopg
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sub : subtract16_glopg
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
|
vdd => vdd,
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s => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15,
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s => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15,
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b => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
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b => res_16& res_17& res_18& res_19& res_20& res_21& res_22& res_23& res_24& res_25& res_26& res_27& res_28& res_29& res_30& res_31,
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a => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15);
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a => res_0& res_1& res_2& res_3& res_4& res_5& res_6& res_7& res_8& res_9& res_10& res_11& res_12& res_13& res_14& res_15);
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reg1 : reg16_glopf
|
reg1 : reg16_glopf
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
q => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
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q => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
|
clr => clr,
|
clr => clr,
|
en => en,
|
en => en,
|
d => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15);
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d => kout2_0& kout2_1& kout2_2& kout2_3& kout2_4& kout2_5& kout2_6& kout2_7& kout2_8& kout2_9& kout2_10& kout2_11& kout2_12& kout2_13& kout2_14& kout2_15);
|
reg2 : reg16_glopf
|
reg2 : reg16_glopf
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
q => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15,
|
q => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15,
|
clr => clr,
|
clr => clr,
|
en => en,
|
en => en,
|
d => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15);
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d => dif_0& dif_1& dif_2& dif_3& dif_4& dif_5& dif_6& dif_7& dif_8& dif_9& dif_10& dif_11& dif_12& dif_13& dif_14& dif_15);
|
add : m16adder_glopg
|
add : m16adder_glopg
|
PORT MAP (
|
PORT MAP (
|
vss => vss,
|
vss => vss,
|
vdd => vdd,
|
vdd => vdd,
|
s => mulout(0)& mulout(1)& mulout(2)& mulout(3)& mulout(4)& mulout(5)& mulout(6)& mulout(7)& mulout(8)& mulout(9)& mulout(10)& mulout(11)& mulout(12)& mulout(13)& mulout(14)& mulout(15),
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s => mulout(0)& mulout(1)& mulout(2)& mulout(3)& mulout(4)& mulout(5)& mulout(6)& mulout(7)& mulout(8)& mulout(9)& mulout(10)& mulout(11)& mulout(12)& mulout(13)& mulout(14)& mulout(15),
|
b => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
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b => r1_0& r1_1& r1_2& r1_3& r1_4& r1_5& r1_6& r1_7& r1_8& r1_9& r1_10& r1_11& r1_12& r1_13& r1_14& r1_15,
|
a => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15);
|
a => r2_0& r2_1& r2_2& r2_3& r2_4& r2_5& r2_6& r2_7& r2_8& r2_9& r2_10& r2_11& r2_12& r2_13& r2_14& r2_15);
|
|
|
end VST;
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end VST;
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