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https://opencores.org/ocsvn/structural_vhdl/structural_vhdl/trunk
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-- VHDL structural description generated from `leftshiftregister5`
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-- VHDL structural description generated from `leftshiftregister5`
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-- date : Tue Jul 31 10:16:46 2001
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-- date : Tue Jul 31 10:16:46 2001
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-- Entity Declaration
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-- Entity Declaration
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ENTITY leftshiftregister5 IS
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ENTITY leftshiftregister5 IS
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PORT (
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PORT (
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p : in BIT_VECTOR (16 DOWNTO 0); -- p
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p : in BIT_VECTOR (16 DOWNTO 0); -- p
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q : in BIT; -- q
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q : in BIT; -- q
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r : out BIT_VECTOR (33 DOWNTO 0); -- r
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r : out BIT_VECTOR (33 DOWNTO 0); -- r
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END leftshiftregister5;
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END leftshiftregister5;
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-- Architecture Declaration
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-- Architecture Declaration
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ARCHITECTURE VST OF leftshiftregister5 IS
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ARCHITECTURE VST OF leftshiftregister5 IS
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COMPONENT a2_x2
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COMPONENT a2_x2
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port (
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port (
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i0 : in BIT; -- i0
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i0 : in BIT; -- i0
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i1 : in BIT; -- i1
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i1 : in BIT; -- i1
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q : out BIT; -- q
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q : out BIT; -- q
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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COMPONENT zero_x0
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COMPONENT zero_x0
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port (
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port (
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nq : out BIT; -- nq
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nq : out BIT; -- nq
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vdd : in BIT; -- vdd
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vdd : in BIT; -- vdd
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vss : in BIT -- vss
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vss : in BIT -- vss
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);
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);
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END COMPONENT;
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END COMPONENT;
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BEGIN
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BEGIN
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r_0 : zero_x0
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r_0 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(0));
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nq => r(0));
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r_1 : zero_x0
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r_1 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(1));
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nq => r(1));
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r_2 : zero_x0
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r_2 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(2));
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nq => r(2));
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r_3 : zero_x0
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r_3 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(3));
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nq => r(3));
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r_4 : zero_x0
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r_4 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(4));
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nq => r(4));
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r_5 : a2_x2
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r_5 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(5),
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q => r(5),
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i1 => p(0),
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i1 => p(0),
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i0 => q);
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i0 => q);
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r_6 : a2_x2
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r_6 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(6),
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q => r(6),
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i1 => p(1),
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i1 => p(1),
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i0 => q);
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i0 => q);
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r_7 : a2_x2
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r_7 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(7),
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q => r(7),
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i1 => p(2),
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i1 => p(2),
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i0 => q);
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i0 => q);
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r_8 : a2_x2
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r_8 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(8),
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q => r(8),
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i1 => p(3),
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i1 => p(3),
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i0 => q);
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i0 => q);
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r_9 : a2_x2
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r_9 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(9),
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q => r(9),
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i1 => p(4),
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i1 => p(4),
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i0 => q);
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i0 => q);
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r_10 : a2_x2
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r_10 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(10),
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q => r(10),
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i1 => p(5),
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i1 => p(5),
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i0 => q);
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i0 => q);
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r_11 : a2_x2
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r_11 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(11),
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q => r(11),
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i1 => p(6),
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i1 => p(6),
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i0 => q);
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i0 => q);
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r_12 : a2_x2
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r_12 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(12),
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q => r(12),
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i1 => p(7),
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i1 => p(7),
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i0 => q);
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i0 => q);
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r_13 : a2_x2
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r_13 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(13),
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q => r(13),
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i1 => p(8),
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i1 => p(8),
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i0 => q);
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i0 => q);
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r_14 : a2_x2
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r_14 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(14),
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q => r(14),
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i1 => p(9),
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i1 => p(9),
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i0 => q);
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i0 => q);
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r_15 : a2_x2
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r_15 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(15),
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q => r(15),
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i1 => p(10),
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i1 => p(10),
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i0 => q);
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i0 => q);
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r_16 : a2_x2
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r_16 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(16),
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q => r(16),
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i1 => p(11),
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i1 => p(11),
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i0 => q);
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i0 => q);
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r_17 : a2_x2
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r_17 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(17),
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q => r(17),
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i1 => p(12),
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i1 => p(12),
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i0 => q);
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i0 => q);
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r_18 : a2_x2
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r_18 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(18),
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q => r(18),
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i1 => p(13),
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i1 => p(13),
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i0 => q);
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i0 => q);
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r_19 : a2_x2
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r_19 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(19),
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q => r(19),
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i1 => p(14),
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i1 => p(14),
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i0 => q);
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i0 => q);
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r_20 : a2_x2
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r_20 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(20),
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q => r(20),
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i1 => p(15),
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i1 => p(15),
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i0 => q);
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i0 => q);
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r_21 : a2_x2
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r_21 : a2_x2
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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q => r(21),
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q => r(21),
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i1 => p(16),
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i1 => p(16),
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i0 => q);
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i0 => q);
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r_22 : zero_x0
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r_22 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(22));
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nq => r(22));
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r_23 : zero_x0
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r_23 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(23));
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nq => r(23));
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r_24 : zero_x0
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r_24 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(24));
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nq => r(24));
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r_25 : zero_x0
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r_25 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(25));
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nq => r(25));
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r_26 : zero_x0
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r_26 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(26));
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nq => r(26));
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r_27 : zero_x0
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r_27 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(27));
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nq => r(27));
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r_28 : zero_x0
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r_28 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(28));
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nq => r(28));
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r_29 : zero_x0
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r_29 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(29));
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nq => r(29));
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r_30 : zero_x0
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r_30 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(30));
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nq => r(30));
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r_31 : zero_x0
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r_31 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(31));
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nq => r(31));
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r_32 : zero_x0
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r_32 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(32));
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nq => r(32));
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r_33 : zero_x0
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r_33 : zero_x0
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PORT MAP (
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PORT MAP (
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vss => vss,
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vss => vss,
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vdd => vdd,
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vdd => vdd,
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nq => r(33));
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nq => r(33));
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end VST;
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end VST;
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