--===========================================================================--
|
--===========================================================================--
|
--
|
--
|
-- S Y N T H E Z I A B L E miniUART C O R E
|
-- S Y N T H E Z I A B L E miniUART C O R E
|
--
|
--
|
-- www.OpenCores.Org - January 2000
|
-- www.OpenCores.Org - January 2000
|
-- This core adheres to the GNU public license
|
-- This core adheres to the GNU public license
|
--
|
--
|
-- Design units : miniUART core for the System68
|
-- Design units : miniUART core for the System68
|
--
|
--
|
-- File name : miniuart2.vhd
|
-- File name : miniuart2.vhd
|
--
|
--
|
-- Purpose : Implements an miniUART device for communication purposes
|
-- Purpose : Implements an miniUART device for communication purposes
|
-- between the CPU68 processor and the Host computer through
|
-- between the CPU68 processor and the Host computer through
|
-- an RS-232 communication protocol.
|
-- an RS-232 communication protocol.
|
--
|
--
|
-- Dependencies : ieee.std_logic_1164
|
-- Dependencies : ieee.std_logic_1164
|
-- ieee.numeric_std
|
-- ieee.numeric_std
|
--
|
--
|
--===========================================================================--
|
--===========================================================================--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revision list
|
-- Revision list
|
-- Version Author Date Changes
|
-- Version Author Date Changes
|
--
|
--
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- 0.1 Ovidiu Lupas 15 January 2000 New model
|
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
|
-- 1.0 Ovidiu Lupas January 2000 Synthesis optimizations
|
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
|
-- 2.0 Ovidiu Lupas April 2000 Bugs removed - RSBusCtrl
|
-- the RSBusCtrl did not process all possible situations
|
-- the RSBusCtrl did not process all possible situations
|
--
|
--
|
-- olupas@opencores.org
|
-- olupas@opencores.org
|
--
|
--
|
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
|
-- 3.0 John Kent October 2002 Changed Status bits to match mc6805
|
-- Added CTS, RTS, Baud rate control
|
-- Added CTS, RTS, Baud rate control
|
-- & Software Reset
|
-- & Software Reset
|
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
|
-- 3.1 John Kent 5 January 2003 Added Word Format control a'la mc6850
|
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
|
-- 3.2 John Kent 19 July 2003 Latched Data input to UART
|
-- 3.3 John Kent 16 January 2004 Integrated clkunit in rxunit & txunit
|
-- 3.3 John Kent 16 January 2004 Integrated clkunit in rxunit & txunit
|
-- Now has external TX 7 RX Baud Clock
|
-- Now has external TX 7 RX Baud Clock
|
-- inputs like the MC6850...
|
-- inputs like the MC6850...
|
-- also supports x1 clock and DCD.
|
-- also supports x1 clock and DCD.
|
--
|
--
|
-- dilbert57@opencores.org
|
-- dilbert57@opencores.org
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Entity for miniUART Unit - 9600 baudrate --
|
-- Entity for miniUART Unit - 9600 baudrate --
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
entity miniUART is
|
entity miniUART is
|
port (
|
port (
|
--
|
--
|
-- CPU signals
|
-- CPU signals
|
--
|
--
|
clk : in Std_Logic; -- System Clock
|
clk : in Std_Logic; -- System Clock
|
rst : in Std_Logic; -- Reset input (active high)
|
rst : in Std_Logic; -- Reset input (active high)
|
cs : in Std_Logic; -- miniUART Chip Select
|
cs : in Std_Logic; -- miniUART Chip Select
|
rw : in Std_Logic; -- Read / Not Write
|
rw : in Std_Logic; -- Read / Not Write
|
irq : out Std_Logic; -- Interrupt
|
irq : out Std_Logic; -- Interrupt
|
Addr : in Std_Logic; -- Register Select
|
Addr : in Std_Logic; -- Register Select
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataIn : in Std_Logic_Vector(7 downto 0); -- Data Bus In
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
DataOut : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
|
--
|
--
|
-- Uart Signals
|
-- Uart Signals
|
--
|
--
|
RxC : in Std_Logic; -- Receive Baud Clock
|
RxC : in Std_Logic; -- Receive Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
TxC : in Std_Logic; -- Transmit Baud Clock
|
RxD : in Std_Logic; -- Receive Data
|
RxD : in Std_Logic; -- Receive Data
|
TxD : out Std_Logic; -- Transmit Data
|
TxD : out Std_Logic; -- Transmit Data
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
DCD_n : in Std_Logic; -- Data Carrier Detect
|
CTS_n : in Std_Logic; -- Clear To Send
|
CTS_n : in Std_Logic; -- Clear To Send
|
RTS_n : out Std_Logic ); -- Request To send
|
RTS_n : out Std_Logic ); -- Request To send
|
end; --================== End of entity ==============================--
|
end; --================== End of entity ==============================--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Architecture for miniUART Controller Unit
|
-- Architecture for miniUART Controller Unit
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
architecture uart of miniUART is
|
architecture uart of miniUART is
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Signals
|
-- Signals
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
signal RxData : Std_Logic_Vector(7 downto 0); --
|
signal RxData : Std_Logic_Vector(7 downto 0); --
|
signal TxData : Std_Logic_Vector(7 downto 0); --
|
signal TxData : Std_Logic_Vector(7 downto 0); --
|
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
|
signal StatReg : Std_Logic_Vector(7 downto 0); -- status register
|
-- StatReg detailed
|
-- StatReg detailed
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
|
-- Irq | PErr | ORErr | FErr | CTS | DCD | TBufE | DRdy |
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
|
signal CtrlReg : Std_Logic_Vector(7 downto 0); -- control register
|
-- CtrlReg detailed
|
-- CtrlReg detailed
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-- RxIEnb |TxCtl(1)|TxCtl(0)|WdFmt(2)|WdFmt(1)|WdFmt(0)|BdCtl(1)|BdCtl(0)|
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-----------+--------+--------+--------+--------+--------+--------+--------+
|
-- RxIEnb
|
-- RxIEnb
|
-- 0 - Rx Interrupt disabled
|
-- 0 - Rx Interrupt disabled
|
-- 1 - Rx Interrupt enabled
|
-- 1 - Rx Interrupt enabled
|
-- TxCtl
|
-- TxCtl
|
-- 0 1 - Tx Interrupt Enable
|
-- 0 1 - Tx Interrupt Enable
|
-- 1 0 - RTS high
|
-- 1 0 - RTS high
|
-- WdFmt
|
-- WdFmt
|
-- 0 0 0 - 7 data, even parity, 2 stop
|
-- 0 0 0 - 7 data, even parity, 2 stop
|
-- 0 0 1 - 7 data, odd parity, 2 stop
|
-- 0 0 1 - 7 data, odd parity, 2 stop
|
-- 0 1 0 - 7 data, even parity, 1 stop
|
-- 0 1 0 - 7 data, even parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 0 1 1 - 7 data, odd parity, 1 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 0 - 8 data, no parity, 2 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 0 1 - 8 data, no parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 0 - 8 data, even parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- 1 1 1 - 8 data, odd parity, 1 stop
|
-- BdCtl
|
-- BdCtl
|
-- 0 0 - Baud Clk divide by 1
|
-- 0 0 - Baud Clk divide by 1
|
-- 0 1 - Baud Clk divide by 16
|
-- 0 1 - Baud Clk divide by 16
|
-- 1 0 - Baud Clk divide by 64
|
-- 1 0 - Baud Clk divide by 64
|
-- 1 1 - reset
|
-- 1 1 - reset
|
|
|
signal TxDbit : Std_Logic; -- Transmit data bit
|
signal TxDbit : Std_Logic; -- Transmit data bit
|
signal DRdy : Std_Logic; -- Receive Data ready
|
signal DRdy : Std_Logic; -- Receive Data ready
|
signal TBufE : Std_Logic; -- Transmit buffer empty
|
signal TBufE : Std_Logic; -- Transmit buffer empty
|
signal FErr : Std_Logic; -- Frame error
|
signal FErr : Std_Logic; -- Frame error
|
signal OErr : Std_Logic; -- Output error
|
signal OErr : Std_Logic; -- Output error
|
signal PErr : Std_Logic; -- Parity Error
|
signal PErr : Std_Logic; -- Parity Error
|
signal TxIEnb : Std_Logic; -- Transmit interrupt enable
|
signal TxIEnb : Std_Logic; -- Transmit interrupt enable
|
signal Read : Std_Logic; -- Read receive buffer
|
signal Read : Std_Logic; -- Read receive buffer
|
signal Load : Std_Logic; -- Load transmit buffer
|
signal Load : Std_Logic; -- Load transmit buffer
|
signal ReadCS : Std_Logic; -- Read Status register
|
signal ReadCS : Std_Logic; -- Read Status register
|
signal LoadCS : Std_Logic; -- Load Control register
|
signal LoadCS : Std_Logic; -- Load Control register
|
signal Reset : Std_Logic; -- Reset (Software & Hardware)
|
signal Reset : Std_Logic; -- Reset (Software & Hardware)
|
signal RxRst : Std_Logic; -- Receive Reset (Software & Hardware)
|
signal RxRst : Std_Logic; -- Receive Reset (Software & Hardware)
|
signal TxRst : Std_Logic; -- Transmit Reset (Software & Hardware)
|
signal TxRst : Std_Logic; -- Transmit Reset (Software & Hardware)
|
signal DCDDel : Std_Logic; -- Delayed DCD_n
|
signal DCDDel : Std_Logic; -- Delayed DCD_n
|
signal DCDEdge : Std_Logic; -- Rising DCD_N Edge Pulse
|
signal DCDEdge : Std_Logic; -- Rising DCD_N Edge Pulse
|
signal DCDState : Std_Logic; -- DCD Reset sequencer
|
signal DCDState : Std_Logic; -- DCD Reset sequencer
|
signal DCDInt : Std_Logic; -- DCD Interrupt
|
signal DCDInt : Std_Logic; -- DCD Interrupt
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Receive Unit
|
-- Receive Unit
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
component RxUnit
|
component RxUnit
|
port (
|
port (
|
Clk : in Std_Logic; -- Clock signal
|
Clk : in Std_Logic; -- Clock signal
|
Reset : in Std_Logic; -- Reset input
|
Reset : in Std_Logic; -- Reset input
|
ReadD : in Std_Logic; -- Read data signal
|
ReadD : in Std_Logic; -- Read data signal
|
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
|
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
|
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
|
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
|
RxClk : in Std_Logic; -- RS-232 clock input
|
RxClk : in Std_Logic; -- RS-232 clock input
|
RxDat : in Std_Logic; -- RS-232 data input
|
RxDat : in Std_Logic; -- RS-232 data input
|
FRErr : out Std_Logic; -- Status signal
|
FRErr : out Std_Logic; -- Status signal
|
ORErr : out Std_Logic; -- Status signal
|
ORErr : out Std_Logic; -- Status signal
|
PAErr : out Std_logic; -- Status signal
|
PAErr : out Std_logic; -- Status signal
|
DARdy : out Std_Logic; -- Status signal
|
DARdy : out Std_Logic; -- Status signal
|
DAOut : out Std_Logic_Vector(7 downto 0));
|
DAOut : out Std_Logic_Vector(7 downto 0));
|
end component;
|
end component;
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Transmitter Unit
|
-- Transmitter Unit
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
component TxUnit
|
component TxUnit
|
port (
|
port (
|
Clk : in Std_Logic; -- Clock signal
|
Clk : in Std_Logic; -- Clock signal
|
Reset : in Std_Logic; -- Reset input
|
Reset : in Std_Logic; -- Reset input
|
LoadD : in Std_Logic; -- Load transmit data
|
LoadD : in Std_Logic; -- Load transmit data
|
DAIn : in Std_Logic_Vector(7 downto 0);
|
DAIn : in Std_Logic_Vector(7 downto 0);
|
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
|
WdFmt : in Std_Logic_Vector(2 downto 0); -- word format
|
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
|
BdFmt : in Std_Logic_Vector(1 downto 0); -- baud format
|
TxClk : in Std_Logic; -- Enable input
|
TxClk : in Std_Logic; -- Enable input
|
TxDat : out Std_Logic; -- RS-232 data output
|
TxDat : out Std_Logic; -- RS-232 data output
|
TBE : out Std_Logic ); -- Tx buffer empty
|
TBE : out Std_Logic ); -- Tx buffer empty
|
end component;
|
end component;
|
begin
|
begin
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Instantiation of internal components
|
-- Instantiation of internal components
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
RxDev : RxUnit port map (
|
RxDev : RxUnit port map (
|
Clk => clk,
|
Clk => clk,
|
Reset => RxRst,
|
Reset => RxRst,
|
ReadD => Read,
|
ReadD => Read,
|
WdFmt => CtrlReg(4 downto 2),
|
WdFmt => CtrlReg(4 downto 2),
|
BdFmt => CtrlReg(1 downto 0),
|
BdFmt => CtrlReg(1 downto 0),
|
RxClk => RxC,
|
RxClk => RxC,
|
RxDat => RxD,
|
RxDat => RxD,
|
FRErr => FErr,
|
FRErr => FErr,
|
ORErr => OErr,
|
ORErr => OErr,
|
PAErr => PErr,
|
PAErr => PErr,
|
DARdy => DRdy,
|
DARdy => DRdy,
|
DAOut => RxData
|
DAOut => RxData
|
);
|
);
|
|
|
|
|
TxDev : TxUnit port map (
|
TxDev : TxUnit port map (
|
Clk => clk,
|
Clk => clk,
|
Reset => TxRst,
|
Reset => TxRst,
|
LoadD => Load,
|
LoadD => Load,
|
DAIn => TxData,
|
DAIn => TxData,
|
WdFmt => CtrlReg(4 downto 2),
|
WdFmt => CtrlReg(4 downto 2),
|
BdFmt => CtrlReg(1 downto 0),
|
BdFmt => CtrlReg(1 downto 0),
|
TxClk => TxC,
|
TxClk => TxC,
|
TxDat => TxDbit,
|
TxDat => TxDbit,
|
TBE => TBufE
|
TBE => TBufE
|
);
|
);
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Implements the controller for Rx&Tx units
|
-- Implements the controller for Rx&Tx units
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
|
miniUart_Status : process(clk, Reset, CtrlReg, TxIEnb,
|
DRdy, TBufE, DCD_n, CTS_n, DCDInt,
|
DRdy, TBufE, DCD_n, CTS_n, DCDInt,
|
FErr, OErr, PErr )
|
FErr, OErr, PErr )
|
variable Int : Std_Logic;
|
variable Int : Std_Logic;
|
begin
|
begin
|
if Reset = '1' then
|
if Reset = '1' then
|
Int := '0';
|
Int := '0';
|
StatReg <= "00000000";
|
StatReg <= "00000000";
|
irq <= '0';
|
irq <= '0';
|
elsif clk'event and clk='0' then
|
elsif clk'event and clk='0' then
|
Int := (CtrlReg(7) and DRdy) or
|
Int := (CtrlReg(7) and DRdy) or
|
(CtrlReg(7) and DCDInt) or
|
(CtrlReg(7) and DCDInt) or
|
(TxIEnb and TBufE);
|
(TxIEnb and TBufE);
|
StatReg(0) <= DRdy; -- Receive Data Ready
|
StatReg(0) <= DRdy; -- Receive Data Ready
|
StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
|
StatReg(1) <= TBufE and (not CTS_n); -- Transmit Buffer Empty
|
StatReg(2) <= DCDInt; -- Data Carrier Detect
|
StatReg(2) <= DCDInt; -- Data Carrier Detect
|
StatReg(3) <= CTS_n; -- Clear To Send
|
StatReg(3) <= CTS_n; -- Clear To Send
|
StatReg(4) <= FErr; -- Framing error
|
StatReg(4) <= FErr; -- Framing error
|
StatReg(5) <= OErr; -- Overrun error
|
StatReg(5) <= OErr; -- Overrun error
|
StatReg(6) <= PErr; -- Parity error
|
StatReg(6) <= PErr; -- Parity error
|
StatReg(7) <= Int;
|
StatReg(7) <= Int;
|
irq <= Int;
|
irq <= Int;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Transmit control
|
-- Transmit control
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
miniUart_TxControl : process( CtrlReg, TxDbit )
|
miniUart_TxControl : process( CtrlReg, TxDbit )
|
begin
|
begin
|
case CtrlReg(6 downto 5) is
|
case CtrlReg(6 downto 5) is
|
when "00" => -- Disable TX Interrupts, Assert RTS
|
when "00" => -- Disable TX Interrupts, Assert RTS
|
RTS_n <= '0';
|
RTS_n <= '0';
|
TxIEnb <= '0';
|
TxIEnb <= '0';
|
TxD <= TxDbit;
|
TxD <= TxDbit;
|
when "01" => -- Enable TX interrupts, Assert RTS
|
when "01" => -- Enable TX interrupts, Assert RTS
|
RTS_n <= '0';
|
RTS_n <= '0';
|
TxIEnb <= '1';
|
TxIEnb <= '1';
|
TxD <= TxDbit;
|
TxD <= TxDbit;
|
when "10" => -- Disable Tx Interrupts, Clear RTS
|
when "10" => -- Disable Tx Interrupts, Clear RTS
|
RTS_n <= '1';
|
RTS_n <= '1';
|
TxIEnb <= '0';
|
TxIEnb <= '0';
|
TxD <= TxDbit;
|
TxD <= TxDbit;
|
when "11" => -- Disable Tx interrupts, Assert RTS, send break
|
when "11" => -- Disable Tx interrupts, Assert RTS, send break
|
RTS_n <= '0';
|
RTS_n <= '0';
|
TxIEnb <= '0';
|
TxIEnb <= '0';
|
TxD <= '0';
|
TxD <= '0';
|
when others =>
|
when others =>
|
RTS_n <= '0';
|
RTS_n <= '0';
|
TxIEnb <= '0';
|
TxIEnb <= '0';
|
TxD <= TxDbit;
|
TxD <= TxDbit;
|
end case;
|
end case;
|
end process;
|
end process;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Write to control register
|
-- Write to control register
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
miniUart_Control: process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
|
miniUart_Control: process(clk, Reset, cs, rw, Addr, DataIn, CtrlReg, TxData )
|
begin
|
begin
|
if (reset = '1') then
|
if (reset = '1') then
|
TxData <= "00000000";
|
TxData <= "00000000";
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
CtrlReg <= "00000000";
|
CtrlReg <= "00000000";
|
LoadCS <= '0';
|
LoadCS <= '0';
|
ReadCS <= '0';
|
ReadCS <= '0';
|
elsif clk'event and clk='0' then
|
elsif clk'event and clk='0' then
|
if cs = '1' then
|
if cs = '1' then
|
if Addr = '1' then -- Data Register
|
if Addr = '1' then -- Data Register
|
if rw = '0' then -- write data register
|
if rw = '0' then -- write data register
|
TxData <= DataIn;
|
TxData <= DataIn;
|
Load <= '1';
|
Load <= '1';
|
Read <= '0';
|
Read <= '0';
|
else -- read Data Register
|
else -- read Data Register
|
TxData <= TxData;
|
TxData <= TxData;
|
Load <= '0';
|
Load <= '0';
|
Read <= '1';
|
Read <= '1';
|
end if; -- rw
|
end if; -- rw
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
LoadCS <= '0';
|
LoadCS <= '0';
|
ReadCS <= '0';
|
ReadCS <= '0';
|
else -- Control / Status register
|
else -- Control / Status register
|
TxData <= TxData;
|
TxData <= TxData;
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
if rw = '0' then -- write control register
|
if rw = '0' then -- write control register
|
CtrlReg <= DataIn;
|
CtrlReg <= DataIn;
|
LoadCS <= '1';
|
LoadCS <= '1';
|
ReadCS <= '0';
|
ReadCS <= '0';
|
else -- read status Register
|
else -- read status Register
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
LoadCS <= '0';
|
LoadCS <= '0';
|
ReadCS <= '1';
|
ReadCS <= '1';
|
end if; -- rw
|
end if; -- rw
|
end if; -- Addr
|
end if; -- Addr
|
else -- not selected
|
else -- not selected
|
TxData <= TxData;
|
TxData <= TxData;
|
Load <= '0';
|
Load <= '0';
|
Read <= '0';
|
Read <= '0';
|
CtrlReg <= CtrlReg;
|
CtrlReg <= CtrlReg;
|
LoadCS <= '0';
|
LoadCS <= '0';
|
ReadCS <= '0';
|
ReadCS <= '0';
|
|
|
end if; -- cs
|
end if; -- cs
|
end if; -- clk / reset
|
end if; -- clk / reset
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- set data output mux
|
-- set data output mux
|
--
|
--
|
--------------------------------------------------------------
|
--------------------------------------------------------------
|
|
|
miniUart_data_read: process(Addr, StatReg, RxData)
|
miniUart_data_read: process(Addr, StatReg, RxData)
|
begin
|
begin
|
if Addr = '1' then
|
if Addr = '1' then
|
DataOut <= RxData; -- read data register
|
DataOut <= RxData; -- read data register
|
else
|
else
|
DataOut <= StatReg; -- read status register
|
DataOut <= StatReg; -- read status register
|
end if; -- Addr
|
end if; -- Addr
|
end process;
|
end process;
|
|
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- Data Carrier Detect Edge rising edge detect
|
-- Data Carrier Detect Edge rising edge detect
|
--
|
--
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel )
|
miniUart_DCD_edge : process( reset, clk, DCD_n, DCDDel )
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
DCDEdge <= '0';
|
DCDEdge <= '0';
|
DCDDel <= '0';
|
DCDDel <= '0';
|
elsif clk'event and clk = '0' then
|
elsif clk'event and clk = '0' then
|
DCDDel <= DCD_n;
|
DCDDel <= DCD_n;
|
DCDEdge <= DCD_n and (not DCDDel);
|
DCDEdge <= DCD_n and (not DCDDel);
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- Data Carrier Detect Interrupt
|
-- Data Carrier Detect Interrupt
|
--
|
--
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
|
miniUart_DCD_int : process( reset, clk, DCDEdge, DCDState, Read, ReadCS, DCDInt )
|
begin
|
begin
|
if reset = '1' then
|
if reset = '1' then
|
DCDInt <= '0';
|
DCDInt <= '0';
|
DCDState <= '0';
|
DCDState <= '0';
|
elsif clk'event and clk = '0' then
|
elsif clk'event and clk = '0' then
|
if DCDEdge = '1' then
|
if DCDEdge = '1' then
|
DCDInt <= '1';
|
DCDInt <= '1';
|
DCDState <= '0';
|
DCDState <= '0';
|
elsif DCDState = '0' then
|
elsif DCDState = '0' then
|
-- To reset DCD interrupt, First read status
|
-- To reset DCD interrupt, First read status
|
if (ReadCS <= '1') and (DCDInt = '1') then
|
if (ReadCS <= '1') and (DCDInt = '1') then
|
DCDState <= '1';
|
DCDState <= '1';
|
else
|
else
|
DCDState <= '0';
|
DCDState <= '0';
|
end if;
|
end if;
|
DCDInt <= DCDInt;
|
DCDInt <= DCDInt;
|
else -- DCDstate = '1'
|
else -- DCDstate = '1'
|
-- Then read the data register
|
-- Then read the data register
|
if Read <= '1' then
|
if Read <= '1' then
|
DCDState <= '0';
|
DCDState <= '0';
|
DCDInt <= '0';
|
DCDInt <= '0';
|
else
|
else
|
DCDState <= DCDState;
|
DCDState <= DCDState;
|
DCDInt <= DCDInt;
|
DCDInt <= DCDInt;
|
end if;
|
end if;
|
end if; -- DCDState
|
end if; -- DCDState
|
end if; -- clk / reset
|
end if; -- clk / reset
|
end process;
|
end process;
|
|
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
--
|
--
|
-- reset may be hardware or software
|
-- reset may be hardware or software
|
--
|
--
|
---------------------------------------------------------------
|
---------------------------------------------------------------
|
|
|
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
|
miniUart_reset: process(rst, CtrlReg, Reset, DCD_n )
|
begin
|
begin
|
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
|
Reset <= (CtrlReg(1) and CtrlReg(0)) or rst;
|
TxRst <= Reset;
|
TxRst <= Reset;
|
RxRst <= Reset or DCD_n;
|
RxRst <= Reset or DCD_n;
|
end process;
|
end process;
|
|
|
end; --===================== End of architecture =======================--
|
end; --===================== End of architecture =======================--
|
|
|
|
|
