//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// MD5 transactor ////
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//// MD5 transactor ////
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//// ////
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//// ////
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//// This file is part of the SystemC MD5 ////
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//// This file is part of the SystemC MD5 ////
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//// ////
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//// ////
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//// Description: ////
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//// Description: ////
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//// MD5 transactor ////
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//// MD5 transactor ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - done ////
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//// - done ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// - Javier Castillo, jcastilo@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1 2004/09/08 16:24:49 jcastillo
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// Initial release
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//
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#include "systemc.h"
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#include "systemc.h"
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class transactor_ports:public sc_module
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class transactor_ports:public sc_module
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{
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{
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public:
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public:
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// Ports
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// Ports
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sc_in < bool > clk;
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sc_in < bool > clk;
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sc_out < bool > reset;
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sc_out < bool > reset;
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sc_out < bool > load_i;
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sc_out < bool > load_i;
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sc_in < bool > ready_o;
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sc_in < bool > ready_o;
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sc_out < bool > newtext_i;
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sc_out < bool > newtext_i;
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//Input must be padded and in little endian mode
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//Input must be padded and in little endian mode
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sc_out < sc_biguint < 128 > >data_i;
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sc_out < sc_biguint < 128 > >data_i;
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sc_in < sc_biguint < 128 > >data_o;
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sc_in < sc_biguint < 128 > >data_o;
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};
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};
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class rw_task_if:virtual public sc_interface
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class rw_task_if:virtual public sc_interface
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{
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{
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public:
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public:
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//Funciones para el transactor
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//Funciones para el transactor
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virtual void resetea (void) = 0;
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virtual void resetea (void) = 0;
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virtual void new_text (void) = 0;
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virtual void new_text (void) = 0;
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virtual void print_result (void) = 0;
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virtual void print_result (void) = 0;
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virtual void wait_result (void) = 0;
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virtual void hash (sc_uint < 32 > data_4, sc_uint < 32 > data_3,
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virtual void hash (sc_uint < 32 > data_4, sc_uint < 32 > data_3,
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sc_uint < 32 > data_2, sc_uint < 32 > data_1) = 0;
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sc_uint < 32 > data_2, sc_uint < 32 > data_1) = 0;
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virtual void wait_cycles (int cycles) = 0;
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virtual void wait_cycles (int cycles) = 0;
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};
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};
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//Transactor
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//Transactor
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class md5_transactor:public rw_task_if, public transactor_ports
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class md5_transactor:public rw_task_if, public transactor_ports
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{
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{
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public:
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public:
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SC_CTOR (md5_transactor)
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SC_CTOR (md5_transactor)
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{
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{
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cout.unsetf (ios::dec);
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cout.unsetf (ios::dec);
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cout.setf (ios::hex);
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cout.setf (ios::hex);
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cout.setf (ios::showbase);
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cout.setf (ios::showbase);
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}
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}
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void resetea (void)
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void resetea (void)
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{
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{
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reset.write (0);
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reset.write (0);
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wait (clk->posedge_event ());
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wait (clk->posedge_event ());
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reset.write (1);
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reset.write (1);
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cout << "Reseteado" << endl;
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cout << "Reseteado" << endl;
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}
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}
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void new_text ()
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void new_text ()
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{
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{
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newtext_i.write (1);
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newtext_i.write (1);
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wait (clk->posedge_event ());
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wait (clk->posedge_event ());
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newtext_i.write (0);
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newtext_i.write (0);
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}
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}
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void wait_result ()
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{
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wait (ready_o->posedge_event ());
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}
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void print_result ()
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void print_result ()
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{
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{
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sc_biguint < 128 > data_o_var;
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sc_biguint < 128 > data_o_var;
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wait (ready_o->posedge_event ());
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wait (ready_o->posedge_event ());
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data_o_var = data_o.read ();
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data_o_var = data_o.read ();
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cout << "HASH: " << (int) (sc_uint < 32 >) data_o_var.range (127,
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96) << " " <<
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cout << "HASH: " << (int) (sc_uint < 32 >) data_o_var.range (127,96) << " " << (int) (sc_uint < 32 >) data_o_var.range (95,64) << " " << (int) (sc_uint <32 >)
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(int) (sc_uint < 32 >) data_o_var.range (95,
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data_o_var.range (63,32) << " " << (int) (sc_uint <32 >) data_o_var.range (31,0) <<endl;
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64) << " " << (int) (sc_uint <
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32 >)
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data_o_var.range (63,
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32) << " " << (int) (sc_uint <
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32 >) data_o_var.range (31,
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0) <<
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endl;
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}
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}
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void hash (sc_uint < 32 > data_4, sc_uint < 32 > data_3,
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void hash (sc_uint < 32 > data_4, sc_uint < 32 > data_3,
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sc_uint < 32 > data_2, sc_uint < 32 > data_1)
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sc_uint < 32 > data_2, sc_uint < 32 > data_1)
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{
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{
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sc_biguint < 128 > data_t;
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sc_biguint < 128 > data_t;
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wait (clk->posedge_event ());
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wait (clk->posedge_event ());
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load_i.write (1);
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load_i.write (1);
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data_t.range (127, 96) = data_4;
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data_t.range (127, 96) = data_4;
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data_t.range (95, 64) = data_3;
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data_t.range (95, 64) = data_3;
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data_t.range (63, 32) = data_2;
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data_t.range (63, 32) = data_2;
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data_t.range (31, 0) = data_1;
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data_t.range (31, 0) = data_1;
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data_i.write (data_t);
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data_i.write (data_t);
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wait (clk->posedge_event ());
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wait (clk->posedge_event ());
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load_i.write (0);
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load_i.write (0);
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}
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}
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void wait_cycles (int cycles)
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void wait_cycles (int cycles)
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{
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{
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for (int i = 0; i < cycles; i++)
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for (int i = 0; i < cycles; i++)
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{
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{
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wait (clk->posedge_event ());
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wait (clk->posedge_event ());
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}
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}
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}
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}
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};
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};
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