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UART IP CoreSpecification


Author: Jacob Gorban
gorban@opencores.org


Rev. 0.6
 TIME \@ "MMMM d, yyyy" August 11, 2002
This page has been intentionally left blank
Revision History

Rev.DateAuthorDescription0.1Jacob GorbanFirst Draft0.227/5/01Jacob GorbanAdded reset values and other changes.0.323/6/01Jacob GorbanDivisor latch is 16-bit wide update0.417/08/01Jacob GorbanModified port names0.503/12/01Jacob GorbanLSR bits 5,6 clear conditions fixed.
In IIR, THRE was fixed.
Debug registers were added to Registers.
Debug interface was added to Operation.
WISHBONE interface ports width modified and  wb_sel_i signal is added to the list.0.611/08/02Jacob GorbanAdded optional BAUD_O output

Contents


 REF Introduction \h  \* MERGEFORMAT Introduction	………………………………………………	 PAGEREF Introduction \h 1

 REF IOports \h  \* MERGEFORMAT IO ports 	………………………………………………	 PAGEREF IOports \h 2

 REF Clocks \h  \* MERGEFORMAT Clocks 	………………………………………………	 PAGEREF Clocks
 \h 3

 REF Registers \h  \* MERGEFORMAT Registers 	………………………………………………	 PAGEREF Registers \h 4

 REF Operation \h  \* MERGEFORMAT Operation 	………………………………………………	 PAGEREF Operation \h 13

 REF Architecture \h  \* MERGEFORMAT Architecture 	………………………………………………	 PAGEREF Architecture \h 151
Introduction

The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry standard National Semiconductors’ 16550A device.

Features:

WISHBONE interface in 32-bit or 8-bit data bus modes (selectable)
FIFO only operation
Register level and functionality compatibility with NS16550A (but not 16450).
Debug Interface in 32-bit data bus mode.


2
IO ports

2.1 WISHBONE interface signals

PortWidthDirectionDescriptionCLK1InputBlock’s clock inputWB_RST_I1InputAsynchronous ResetWB_ADDR_I5 or 3InputUsed for register selectionWB_SEL_I4InputSelect signalWB_DAT_I32 or 8InputData inputWB_DAT_O32 or 8OutputData outputWB_WE_I1InputWrite or read cycle selectionWB_STB_I1InputSpecifies transfer cycleWB_CYC_I1InputA bus cycle is in progressWB_ACK_O1OutputAcknowledge of a transfer
2.2 Other internal signals

PortWidthDirectionDescriptionINT_O1OutputInterrupt outputBAUD_O1OutputOptional baud rate output signal.
The signal here is the 16 x actual baud rate.
It is enabled if UART_HAS_BAUDRATE_OUTPUT is defined

2.3 External (off-chip) connections

PortWidthDirectionDescriptionSTX_PAD_O1OutputThe serial output signalSRX_PAD_I1InputThe serial input signalRTS_PAD_O1OutputRequest To SendDTR_PAD_O1OutputData Terminal ReadyCTS_PAD_I1InputClear To SendDSR_PAD_I1InputData Set ReadyRI_PAD_I1InputRing IndicatorDCD_PAD_I1InputData Carrier Detect3 
Clocks
Clocks table:

NameSourceRates (MHz)DescriptionMaxMinResolutionclkWISHBONE bus1258Mhz for  1200 bps3.6864 for 115200 bpsWISHBONE clock4
Registers

4.1 Registers list

NameAddressWidthAccessDescriptionReceiver Buffer08RReceiver FIFO outputTransmitter Holding Register (THR)08WTransmit FIFO input HYPERLINK  \l "IER" Interrupt Enable18RWEnable/Mask interrupts generated by the UART HYPERLINK  \l "IIR" Interrupt Identification28RGet interrupt information HYPERLINK  \l "FCR" FIFO Control28WControl FIFO options HYPERLINK  \l "LCR" Line Control Register38RWControl connection HYPERLINK  \l "MCR" Modem Control48WControls modem HYPERLINK  \l "LSR" Line Status58RStatus information HYPERLINK  \l "MSR" Modem Status68RModem Status

In addition, there are 2 Clock Divisor registers that together form one 16-bit. 
The registers can be accessed when the 7th (DLAB) bit of the Line Control Register is set to ‘1’. At this time the above registers at addresses 0-1 can’t be accessed.

NameAddressWidthAccessDescription HYPERLINK  \l "DivisorLatches" Divisor Latch Byte 1 (LSB)08RWThe LSB of the divisor latchDivisor Latch Byte 218RWThe MSB of the divisor latch
When using 32-bit data bus interface, additional read-only registers are available for debug purposes:

NameAddressWidthAccessDescription HYPERLINK  \l "Debug1" Debug 1832RFirst debug register HYPERLINK  \l "Debug2" Debug 21232RSecond debug register

4.2 Interrupt Enable Register (IER)

This register allows enabling and disabling interrupt generation by the UART.

Bit #AccessDescription0RWReceived Data available interrupt
	‘0’ – disabled
	‘1’ – enabled1RWTransmitter Holding Register empty interrupt
	‘0’ – disabled
	‘1’ – enabled2RWReceiver Line Status Interrupt
	‘0’ – disabled
	‘1’ – enabled3RWModem Status Interrupt
	‘0’ – disabled
	‘1’ – enabled7-4RWReserved. Should be logic ‘0’.
Reset Value: 00h

4.3 Interrupt Identification Register (IIR)

The IIR enables the programmer to retrieve what is the current highest priority pending interrupt. 
Bit 0 indicates that an interrupt is pending when it’s logic ‘0’. When it’s ‘1’ – no interrupt is pending.
The following table displays the list of possible interrupts along with the bits they enable, priority, and their source and reset control.

Bit 3Bit 2Bit 1PriorityInterrupt TypeInterrupt SourceInterrupt Reset Control0111stReceiver Line StatusParity, Overrun or Framing errors or Break InterruptReading the Line Status Register0102ndReceiver Data availableFIFO trigger level reachedFIFO drops below trigger level1102ndTimeout IndicationThere’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times.Reading from the FIFO (Receiver Buffer Register)0013rdTransmitter Holding Register emptyTransmitter Holding Register EmptyWriting to the Transmitter Holding Register or reading IIR.0004thModem StatusCTS, DSR, RI or DCD.Reading the Modem status register.
Bits 4 and 5: Logic ‘0’.
Bits 6 and 7: Logic ‘1’ for compatibility reason.

Reset Value: C1h

4.4 FIFO Control Register (FCR)

The FCR allows selection of the FIFO trigger level (the number of bytes in FIFO required to enable the Received Data Available interrupt).  In addition, the FIFOs can be cleared using this register. 

Bit #AccessDescription0WIgnored (Used to enable FIFOs in NS16550D). Since this UART only supports FIFO mode, this bit is ignored.1WWriting a ‘1’ to bit 1 clears the Receiver FIFO and resets its logic. But it doesn’t clear the shift register, i.e. receiving of the current character continues.2WWriting a ‘1’ to bit 2 clears the Transmitter FIFO and resets its logic. The shift register is not cleared, i.e. transmitting of the current character continues.5-3WIgnored7-6WDefine the Receiver FIFO Interrupt trigger level
	‘00’ – 1 byte
	‘01’ – 4 bytes
	‘10’ – 8 bytes
	‘11’ – 14 bytes
Reset Value : 11000000b

4.5 Line Control Register (LCR)

The line control register allows the specification of the format of the asynchronous data communication used. A bit in the register also allows access to the Divisor Latches, which define the baud rate. Reading from the register is allowed to check the current settings of the communication.

Bit #AccessDescription1-0RWSelect number of bits in each character
	‘00’ – 5 bits
	‘01’ – 6 bits
	‘10’ – 7 bits
	‘11’ – 8 bits2RWSpecify the number of generated stop bits
	‘0’ – 1 stop bit
	‘1’ – 1.5 stop bits when 5-bit character length selected and 
		2 bits otherwise

Note that the receiver always checks the first stop bit only.3RWParity Enable
	‘0’ – No parity
	‘1’ – Parity bit is generated on each outgoing character and 			is checked on each incoming one.4RWEven Parity select
	‘0’ – Odd number of ‘1’ is transmitted and checked in each word (data and parity combined). In other words, if the data has an even number of ‘1’ in it, then the parity bit is ‘1’.

	‘1’ – Even number of ‘1’ is transmitted in each word.5RWStick Parity bit.
	‘0’ – Stick Parity disabled
	‘1’ - If bits 3 and 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.
6RWBreak Control bit
	‘1’ – the serial out is forced into logic ‘0’ (break state).
	‘0’ – break is disabled7RWDivisor Latch Access bit.
	‘1’ – The divisor latches can be accessed
	‘0’ – The normal registers are accessedReset Value: 00000011b

4.6 Modem Control Register (MCR)

The modem control register allows transferring control signals to a modem connected to the UART.

Bit #AccessDescription0WData Terminal Ready (DTR) signal control
	‘0’ – DTR is ‘1’
	‘1’ – DTR is ‘0’1WRequest To Send (RTS) signal control
	‘0’ – RTS is ‘1’
	‘1’ – RTS is ‘0’2WOut1. In loopback mode, connected Ring Indicator (RI) signal input3WOut2. In loopback mode, connected to Data Carrier Detect (DCD) input.4WLoopback mode
	‘0’ – normal operation
	‘1’ – loopback mode. When in loopback mode, the Serial Output Signal (STX_PAD_O) is set to logic ‘1’. The signal of the transmitter shift register is internally connected to the input of the receiver shift register.
The following connections are made:
DTR (  DSR
RTS ( CTS
Out1 ( RI
Out2 ( DCD
7-5WIgnoredReset Value: 0
4.7 Line Status Register (LSR)

Bit #AccessDescription0RData Ready (DR) indicator.
	‘0’ – No characters in the FIFO
	‘1’ – At least one character has been received and is in the FIFO.1ROverrun Error (OE) indicator
	‘1’ – If the FIFO is full and another character has been received in the receiver shift register. If another character is starting to arrive, it will overwrite the data in the shift register but the FIFO will remain intact. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No overrun state2RParity Error (PE) indicator
	‘1’ – The character that is currently at the top of the FIFO has been received with parity error. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No parity error in the current character3RFraming Error (FE) indicator
	‘1’ – The received character at the top of the FIFO did not have a valid stop bit. Of course, generally, it might be that all the following data is corrupt. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No framing error in the current character 4RBreak Interrupt (BI) indicator
	‘1’ –A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive next character. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No break condition in the current character5RTransmit FIFO is empty.
	‘1’ – The transmitter FIFO is empty. Generates Transmitter Holding Register Empty interrupt. The bit is cleared when data is being been written to the transmitter FIFO.
	‘0’ – Otherwise6RTransmitter Empty indicator.
	‘1’ – Both the transmitter FIFO and transmitter shift register are empty. The bit is cleared when data is being been written to the transmitter FIFO.
	‘0’ – Otherwise7R	‘1’ – At least one parity error, framing error or break indications have been received and are inside the FIFO. The bit is cleared upon reading from the register.
	‘0’ – Otherwise.
4.8 Modem Status Register (MSR)

The register displays the current state of the modem control lines. Also, four bits also provide an indication in the state of one of the modem status lines. These bits are set to ‘1’ when a change in corresponding line has been detected and they are reset when the register is being read.

Bit #AccessDescription0RDelta Clear To Send (DCTS) indicator
	‘1’ – The CTS line has changed its state.1RDelta Data Set Ready (DDSR) indicator
	‘1’ – The DSR line has changed its state.2RTrailing Edge of Ring Indicator (TERI) detector. The RI line has changed its state from low to high state.3RDelta Data Carrier Detect (DDCD) indicator
	‘1’ – The DCD line has changed its state.4RComplement of the CTS input or equals to RTS in loopback mode.5RComplement of the DSR input or equals to DTR in loopback mode.6RComplement of the RI input or equals to Out1 in loopback mode.7RComplement of the DCD input or equals to Out2 in loopback mode.
4.9 Divisor Latches 

The divisor latches can be accessed by setting the 7th bit of LCR to ‘1’. You should restore this bit to ‘0’ after setting the divisor latches in order to restore access to the other registers that occupy the same addresses. The 2 bytes form one 16-bit register, which is internally accessed as a single number. You should therefore set all 2 bytes of the register to ensure normal operation. The register is set to the default value of 0 on reset, which disables all serial I/O operations in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed) / (16 x desired baud rate).
The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.

4.10 Debug 1

This register is only available when the core has 32-bit data bus and 5-bit address bus.
It is read only and is provided for debugging purposes of chip testing as it is not part of the original UART16550 device specifications. Reading from the does not influence core’s bahaviour. 

Bit #AccessDescription7-0RLine Status Register value.11-8RInterrupt Enable Register value (bits 3-0).15-12RInterrupt Identifier Register value (bits 3-0).23-16RLine Control Register value.31-24RModem Status Register value.
4.11 Debug 2

This register is only available when the core has 32-bit data bus and 5-bit address bus.
It is read only and is provided for debugging purposes of chip testing as it is not part of the original UART16550 device specifications. Reading from the does not influence core’s bahaviour. 

Bit #AccessDescription2-0RTransmitter FSM state7-3RNumber of characters in Transmitter FIFO (tf_count)11-8RReceiver FSM state16-12RNumber of characters in Receiver FIFO (rf_count)18-17RModem Control Register value (bits 4-0)23-19RFIFO Control Register value (bits 7-6)31-24RReserved. Returned value is 0.
5
Operation

This UART core is very similar in operation to the standard 16550 UART chip with the main exception being that only the FIFO mode is supported. The scratch register is removed, as it serves no purpose.

This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode.

The 32-bit mode is fully WISHBONE compatible and it uses the WISHBONE [SEL_I] signal to properly receive and return 8-bit data on 32-bit data bus. The 8-bit version might have problems in various WISHBONE implementations because a 32-bit master reading from 8-bit bus can expect data on different bytes of the 4-byte word, depending on the register address.
Also, in 32-bit data bus mode, the [ADR_I] is 5 and not 3 bits wide.  

In addition, in the 32-bit data bus mode a debug interface is present in the system. This interface has 2 32-bit registers that can be read to provide non-intrusive look into the core’s registers and other internal values of importance. 

The selection between 32- and 8-bits data bus  modes is performed by defining DATA_BUS_WIDTH_8 in uart_defines.v, uart_top.v or on the compiler/synthesizer tool command line. 

5.1 Initialization 

Upon reset the core performs the following tasks:

The receiver and transmitter FIFOs are cleared.
The receiver and transmitter shift registers are cleared
The Divisor Latch register is set to 0.
The Line Control Register is set to communication of 8 bits of data, no parity, 1 stop bit. 
All interrupts are disabled in the Interrupt Enable Register.

For proper operation, perform the following:

Set the Line Control Register to the desired line control parameters. Set bit 7 to ‘1’ to allow access to the Divisor Latches.
Set the Divisor Latches, MSB first, LSB next. 
Set bit 7 of LCR to ‘0’ to disable access to Divisor Latches. At this time the transmission engine starts working and data can be sent and received.
Set the FIFO trigger level. Generally, higher trigger level values produce less interrupt to the system, so setting it to 14 bytes is recommended if the system responds fast enough.
Enable desired interrupts by setting appropriate bits in the Interrupt Enable register.

Remember that (Input Clock Speed)/(Divisor Latch value) = 16 x the communication baud rate. Since the protocol is asynchronous and the sampling of the bits is performed in the perceived middle of the bit time, it is highly immune to small differences in the clocks of the sending and receiving sides, yet no such assumption should be made when calculating the Divisor Latch values.



6
Architecture

The core implements the WISNBONE SoC bus interface for communication with the system. It has an 8-bit data bus for compatibility reason. The core requires one interrupt. It requires 2 pads in the chip (serial in and serial out) and, optionally, another six modem control signals, which can otherwise be implemented using general purpose I/Os on the chip.

The block diagram of the core is on the following page.



OpenCores	UART16550 core specifications	 DATE  \* MERGEFORMAT 8/11/2002

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.1 Preliminary	 PAGE  Š of  SECTIONPAGES2

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.6	 PAGE i 

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.6	 PAGE 1 of  SECTIONPAGES16


Figure  SEQ Figure \* ARABIC 1 - Block Diagram of the UART core




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UART IP CoreSpecification


Author: Jacob Gorban
gorban@opencores.org


Rev. 0.6
 TIME \@ "MMMM d, yyyy" August 11, 2002
This page has been intentionally left blank
Revision History

Rev.DateAuthorDescription0.1Jacob GorbanFirst Draft0.227/5/01Jacob GorbanAdded reset values and other changes.0.323/6/01Jacob GorbanDivisor latch is 16-bit wide update0.417/08/01Jacob GorbanModified port names0.503/12/01Jacob GorbanLSR bits 5,6 clear conditions fixed.
In IIR, THRE was fixed.
Debug registers were added to Registers.
Debug interface was added to Operation.
WISHBONE interface ports width modified and  wb_sel_i signal is added to the list.0.611/08/02Jacob GorbanAdded optional BAUD_O output

Contents


 REF Introduction \h  \* MERGEFORMAT Introduction	………………………………………………	 PAGEREF Introduction \h 1

 REF IOports \h  \* MERGEFORMAT IO ports 	………………………………………………	 PAGEREF IOports \h 2

 REF Clocks \h  \* MERGEFORMAT Clocks 	………………………………………………	 PAGEREF Clocks
 \h 3

 REF Registers \h  \* MERGEFORMAT Registers 	………………………………………………	 PAGEREF Registers \h 4

 REF Operation \h  \* MERGEFORMAT Operation 	………………………………………………	 PAGEREF Operation \h 13

 REF Architecture \h  \* MERGEFORMAT Architecture 	………………………………………………	 PAGEREF Architecture \h 151
Introduction

The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. This core is designed to be maximally compatible with the industry standard National Semiconductors’ 16550A device.

Features:

WISHBONE interface in 32-bit or 8-bit data bus modes (selectable)
FIFO only operation
Register level and functionality compatibility with NS16550A (but not 16450).
Debug Interface in 32-bit data bus mode.


2
IO ports

2.1 WISHBONE interface signals

PortWidthDirectionDescriptionCLK1InputBlock’s clock inputWB_RST_I1InputAsynchronous ResetWB_ADDR_I5 or 3InputUsed for register selectionWB_SEL_I4InputSelect signalWB_DAT_I32 or 8InputData inputWB_DAT_O32 or 8OutputData outputWB_WE_I1InputWrite or read cycle selectionWB_STB_I1InputSpecifies transfer cycleWB_CYC_I1InputA bus cycle is in progressWB_ACK_O1OutputAcknowledge of a transfer
2.2 Other internal signals

PortWidthDirectionDescriptionINT_O1OutputInterrupt outputBAUD_O1OutputOptional baud rate output signal.
The signal here is the 16 x actual baud rate.
It is enabled if UART_HAS_BAUDRATE_OUTPUT is defined

2.3 External (off-chip) connections

PortWidthDirectionDescriptionSTX_PAD_O1OutputThe serial output signalSRX_PAD_I1InputThe serial input signalRTS_PAD_O1OutputRequest To SendDTR_PAD_O1OutputData Terminal ReadyCTS_PAD_I1InputClear To SendDSR_PAD_I1InputData Set ReadyRI_PAD_I1InputRing IndicatorDCD_PAD_I1InputData Carrier Detect3 
Clocks
Clocks table:

NameSourceRates (MHz)DescriptionMaxMinResolutionclkWISHBONE bus1258Mhz for  1200 bps3.6864 for 115200 bpsWISHBONE clock4
Registers

4.1 Registers list

NameAddressWidthAccessDescriptionReceiver Buffer08RReceiver FIFO outputTransmitter Holding Register (THR)08WTransmit FIFO input HYPERLINK  \l "IER" Interrupt Enable18RWEnable/Mask interrupts generated by the UART HYPERLINK  \l "IIR" Interrupt Identification28RGet interrupt information HYPERLINK  \l "FCR" FIFO Control28WControl FIFO options HYPERLINK  \l "LCR" Line Control Register38RWControl connection HYPERLINK  \l "MCR" Modem Control48WControls modem HYPERLINK  \l "LSR" Line Status58RStatus information HYPERLINK  \l "MSR" Modem Status68RModem Status

In addition, there are 2 Clock Divisor registers that together form one 16-bit. 
The registers can be accessed when the 7th (DLAB) bit of the Line Control Register is set to ‘1’. At this time the above registers at addresses 0-1 can’t be accessed.

NameAddressWidthAccessDescription HYPERLINK  \l "DivisorLatches" Divisor Latch Byte 1 (LSB)08RWThe LSB of the divisor latchDivisor Latch Byte 218RWThe MSB of the divisor latch
When using 32-bit data bus interface, additional read-only registers are available for debug purposes:

NameAddressWidthAccessDescription HYPERLINK  \l "Debug1" Debug 1832RFirst debug register HYPERLINK  \l "Debug2" Debug 21232RSecond debug register

4.2 Interrupt Enable Register (IER)

This register allows enabling and disabling interrupt generation by the UART.

Bit #AccessDescription0RWReceived Data available interrupt
	‘0’ – disabled
	‘1’ – enabled1RWTransmitter Holding Register empty interrupt
	‘0’ – disabled
	‘1’ – enabled2RWReceiver Line Status Interrupt
	‘0’ – disabled
	‘1’ – enabled3RWModem Status Interrupt
	‘0’ – disabled
	‘1’ – enabled7-4RWReserved. Should be logic ‘0’.
Reset Value: 00h

4.3 Interrupt Identification Register (IIR)

The IIR enables the programmer to retrieve what is the current highest priority pending interrupt. 
Bit 0 indicates that an interrupt is pending when it’s logic ‘0’. When it’s ‘1’ – no interrupt is pending.
The following table displays the list of possible interrupts along with the bits they enable, priority, and their source and reset control.

Bit 3Bit 2Bit 1PriorityInterrupt TypeInterrupt SourceInterrupt Reset Control0111stReceiver Line StatusParity, Overrun or Framing errors or Break InterruptReading the Line Status Register0102ndReceiver Data availableFIFO trigger level reachedFIFO drops below trigger level1102ndTimeout IndicationThere’s at least 1 character in the FIFO but no character has been input to the FIFO or read from it for the last 4 Char times.Reading from the FIFO (Receiver Buffer Register)0013rdTransmitter Holding Register emptyTransmitter Holding Register EmptyWriting to the Transmitter Holding Register or reading IIR.0004thModem StatusCTS, DSR, RI or DCD.Reading the Modem status register.
Bits 4 and 5: Logic ‘0’.
Bits 6 and 7: Logic ‘1’ for compatibility reason.

Reset Value: C1h

4.4 FIFO Control Register (FCR)

The FCR allows selection of the FIFO trigger level (the number of bytes in FIFO required to enable the Received Data Available interrupt).  In addition, the FIFOs can be cleared using this register. 

Bit #AccessDescription0WIgnored (Used to enable FIFOs in NS16550D). Since this UART only supports FIFO mode, this bit is ignored.1WWriting a ‘1’ to bit 1 clears the Receiver FIFO and resets its logic. But it doesn’t clear the shift register, i.e. receiving of the current character continues.2WWriting a ‘1’ to bit 2 clears the Transmitter FIFO and resets its logic. The shift register is not cleared, i.e. transmitting of the current character continues.5-3WIgnored7-6WDefine the Receiver FIFO Interrupt trigger level
	‘00’ – 1 byte
	‘01’ – 4 bytes
	‘10’ – 8 bytes
	‘11’ – 14 bytes
Reset Value : 11000000b

4.5 Line Control Register (LCR)

The line control register allows the specification of the format of the asynchronous data communication used. A bit in the register also allows access to the Divisor Latches, which define the baud rate. Reading from the register is allowed to check the current settings of the communication.

Bit #AccessDescription1-0RWSelect number of bits in each character
	‘00’ – 5 bits
	‘01’ – 6 bits
	‘10’ – 7 bits
	‘11’ – 8 bits2RWSpecify the number of generated stop bits
	‘0’ – 1 stop bit
	‘1’ – 1.5 stop bits when 5-bit character length selected and 
		2 bits otherwise

Note that the receiver always checks the first stop bit only.3RWParity Enable
	‘0’ – No parity
	‘1’ – Parity bit is generated on each outgoing character and 			is checked on each incoming one.4RWEven Parity select
	‘0’ – Odd number of ‘1’ is transmitted and checked in each word (data and parity combined). In other words, if the data has an even number of ‘1’ in it, then the parity bit is ‘1’.

	‘1’ – Even number of ‘1’ is transmitted in each word.5RWStick Parity bit.
	‘0’ – Stick Parity disabled
	‘1’ - If bits 3 and 4 are logic ‘1’, the parity bit is transmitted and checked as logic ‘0’. If bit 3 is ‘1’ and bit 4 is ‘0’ then the parity bit is transmitted and checked as ‘1’.
6RWBreak Control bit
	‘1’ – the serial out is forced into logic ‘0’ (break state).
	‘0’ – break is disabled7RWDivisor Latch Access bit.
	‘1’ – The divisor latches can be accessed
	‘0’ – The normal registers are accessedReset Value: 00000011b

4.6 Modem Control Register (MCR)

The modem control register allows transferring control signals to a modem connected to the UART.

Bit #AccessDescription0WData Terminal Ready (DTR) signal control
	‘0’ – DTR is ‘1’
	‘1’ – DTR is ‘0’1WRequest To Send (RTS) signal control
	‘0’ – RTS is ‘1’
	‘1’ – RTS is ‘0’2WOut1. In loopback mode, connected Ring Indicator (RI) signal input3WOut2. In loopback mode, connected to Data Carrier Detect (DCD) input.4WLoopback mode
	‘0’ – normal operation
	‘1’ – loopback mode. When in loopback mode, the Serial Output Signal (STX_PAD_O) is set to logic ‘1’. The signal of the transmitter shift register is internally connected to the input of the receiver shift register.
The following connections are made:
DTR (  DSR
RTS ( CTS
Out1 ( RI
Out2 ( DCD
7-5WIgnoredReset Value: 0
4.7 Line Status Register (LSR)

Bit #AccessDescription0RData Ready (DR) indicator.
	‘0’ – No characters in the FIFO
	‘1’ – At least one character has been received and is in the FIFO.1ROverrun Error (OE) indicator
	‘1’ – If the FIFO is full and another character has been received in the receiver shift register. If another character is starting to arrive, it will overwrite the data in the shift register but the FIFO will remain intact. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No overrun state2RParity Error (PE) indicator
	‘1’ – The character that is currently at the top of the FIFO has been received with parity error. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No parity error in the current character3RFraming Error (FE) indicator
	‘1’ – The received character at the top of the FIFO did not have a valid stop bit. Of course, generally, it might be that all the following data is corrupt. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No framing error in the current character 4RBreak Interrupt (BI) indicator
	‘1’ –A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive next character. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
	‘0’ – No break condition in the current character5RTransmit FIFO is empty.
	‘1’ – The transmitter FIFO is empty. Generates Transmitter Holding Register Empty interrupt. The bit is cleared when data is being been written to the transmitter FIFO.
	‘0’ – Otherwise6RTransmitter Empty indicator.
	‘1’ – Both the transmitter FIFO and transmitter shift register are empty. The bit is cleared when data is being been written to the transmitter FIFO.
	‘0’ – Otherwise7R	‘1’ – At least one parity error, framing error or break indications have been received and are inside the FIFO. The bit is cleared upon reading from the register.
	‘0’ – Otherwise.
4.8 Modem Status Register (MSR)

The register displays the current state of the modem control lines. Also, four bits also provide an indication in the state of one of the modem status lines. These bits are set to ‘1’ when a change in corresponding line has been detected and they are reset when the register is being read.

Bit #AccessDescription0RDelta Clear To Send (DCTS) indicator
	‘1’ – The CTS line has changed its state.1RDelta Data Set Ready (DDSR) indicator
	‘1’ – The DSR line has changed its state.2RTrailing Edge of Ring Indicator (TERI) detector. The RI line has changed its state from low to high state.3RDelta Data Carrier Detect (DDCD) indicator
	‘1’ – The DCD line has changed its state.4RComplement of the CTS input or equals to RTS in loopback mode.5RComplement of the DSR input or equals to DTR in loopback mode.6RComplement of the RI input or equals to Out1 in loopback mode.7RComplement of the DCD input or equals to Out2 in loopback mode.
4.9 Divisor Latches 

The divisor latches can be accessed by setting the 7th bit of LCR to ‘1’. You should restore this bit to ‘0’ after setting the divisor latches in order to restore access to the other registers that occupy the same addresses. The 2 bytes form one 16-bit register, which is internally accessed as a single number. You should therefore set all 2 bytes of the register to ensure normal operation. The register is set to the default value of 0 on reset, which disables all serial I/O operations in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed) / (16 x desired baud rate).
The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.

4.10 Debug 1

This register is only available when the core has 32-bit data bus and 5-bit address bus.
It is read only and is provided for debugging purposes of chip testing as it is not part of the original UART16550 device specifications. Reading from the does not influence core’s bahaviour. 

Bit #AccessDescription7-0RLine Status Register value.11-8RInterrupt Enable Register value (bits 3-0).15-12RInterrupt Identifier Register value (bits 3-0).23-16RLine Control Register value.31-24RModem Status Register value.
4.11 Debug 2

This register is only available when the core has 32-bit data bus and 5-bit address bus.
It is read only and is provided for debugging purposes of chip testing as it is not part of the original UART16550 device specifications. Reading from the does not influence core’s bahaviour. 

Bit #AccessDescription2-0RTransmitter FSM state7-3RNumber of characters in Transmitter FIFO (tf_count)11-8RReceiver FSM state16-12RNumber of characters in Receiver FIFO (rf_count)18-17RModem Control Register value (bits 4-0)23-19RFIFO Control Register value (bits 7-6)31-24RReserved. Returned value is 0.
5
Operation

This UART core is very similar in operation to the standard 16550 UART chip with the main exception being that only the FIFO mode is supported. The scratch register is removed, as it serves no purpose.

This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode.

The 32-bit mode is fully WISHBONE compatible and it uses the WISHBONE [SEL_I] signal to properly receive and return 8-bit data on 32-bit data bus. The 8-bit version might have problems in various WISHBONE implementations because a 32-bit master reading from 8-bit bus can expect data on different bytes of the 4-byte word, depending on the register address.
Also, in 32-bit data bus mode, the [ADR_I] is 5 and not 3 bits wide.  

In addition, in the 32-bit data bus mode a debug interface is present in the system. This interface has 2 32-bit registers that can be read to provide non-intrusive look into the core’s registers and other internal values of importance. 

The selection between 32- and 8-bits data bus  modes is performed by defining DATA_BUS_WIDTH_8 in uart_defines.v, uart_top.v or on the compiler/synthesizer tool command line. 

5.1 Initialization 

Upon reset the core performs the following tasks:

The receiver and transmitter FIFOs are cleared.
The receiver and transmitter shift registers are cleared
The Divisor Latch register is set to 0.
The Line Control Register is set to communication of 8 bits of data, no parity, 1 stop bit. 
All interrupts are disabled in the Interrupt Enable Register.

For proper operation, perform the following:

Set the Line Control Register to the desired line control parameters. Set bit 7 to ‘1’ to allow access to the Divisor Latches.
Set the Divisor Latches, MSB first, LSB next. 
Set bit 7 of LCR to ‘0’ to disable access to Divisor Latches. At this time the transmission engine starts working and data can be sent and received.
Set the FIFO trigger level. Generally, higher trigger level values produce less interrupt to the system, so setting it to 14 bytes is recommended if the system responds fast enough.
Enable desired interrupts by setting appropriate bits in the Interrupt Enable register.

Remember that (Input Clock Speed)/(Divisor Latch value) = 16 x the communication baud rate. Since the protocol is asynchronous and the sampling of the bits is performed in the perceived middle of the bit time, it is highly immune to small differences in the clocks of the sending and receiving sides, yet no such assumption should be made when calculating the Divisor Latch values.



6
Architecture

The core implements the WISNBONE SoC bus interface for communication with the system. It has an 8-bit data bus for compatibility reason. The core requires one interrupt. It requires 2 pads in the chip (serial in and serial out) and, optionally, another six modem control signals, which can otherwise be implemented using general purpose I/Os on the chip.

The block diagram of the core is on the following page.



OpenCores	UART16550 core specifications	 DATE  \* MERGEFORMAT 8/11/2002

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.1 Preliminary	 PAGE  Š of  SECTIONPAGES2

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.6	 PAGE i 

HYPERLINK "http://www.opencores.org/"www.opencores.org	Rev 0.6	 PAGE 1 of  SECTIONPAGES16


Figure  SEQ Figure \* ARABIC 1 - Block Diagram of the UART core




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