-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Testbench for the T411 system toplevel.
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-- Testbench for the T411 system toplevel.
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--
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--
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-- $Id: tb_t411.vhd,v 1.6 2006-06-05 18:50:45 arniml Exp $
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-- $Id: tb_t411.vhd 179 2009-04-01 19:48:38Z arniml $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t400/
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-- http://www.opencores.org/cvsweb.shtml/t400/
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity tb_t411 is
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entity tb_t411 is
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end tb_t411;
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end tb_t411;
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use work.t400_system_comp_pack.t411;
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use work.t400_system_comp_pack.t411;
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use work.tb_pack.tb_elems;
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use work.tb_pack.tb_elems;
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use work.t400_opt_pack.all;
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use work.t400_opt_pack.all;
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architecture behav of tb_t411 is
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architecture behav of tb_t411 is
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-- 210.4 kHz clock
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-- 210.4 kHz clock
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constant period_c : time := 4.75 us;
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constant period_c : time := 4.75 us;
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signal ck_s : std_logic;
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signal ck_s : std_logic;
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signal reset_n_s : std_logic;
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signal reset_n_s : std_logic;
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signal io_l_s : std_logic_vector(7 downto 0);
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signal io_l_s : std_logic_vector(7 downto 0);
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signal io_d_s : std_logic_vector(1 downto 0);
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signal io_d_s : std_logic_vector(1 downto 0);
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signal io_g_s : std_logic_vector(2 downto 0);
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signal io_g_s : std_logic_vector(2 downto 0);
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signal si_s,
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signal si_s,
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so_s,
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so_s,
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sk_s : std_logic;
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sk_s : std_logic;
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signal vdd_s : std_logic;
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signal vdd_s : std_logic;
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begin
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begin
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vdd_s <= '1';
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vdd_s <= '1';
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reset_n_s <= '1';
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reset_n_s <= '1';
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- DUT
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-- DUT
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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t411_b : t411
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t411_b : t411
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generic map (
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generic map (
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opt_ck_div_g => t400_opt_ck_div_8_c
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opt_ck_div_g => t400_opt_ck_div_8_c
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)
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)
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port map (
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port map (
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ck_i => ck_s,
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ck_i => ck_s,
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ck_en_i => vdd_s,
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ck_en_i => vdd_s,
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reset_n_i => reset_n_s,
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reset_n_i => reset_n_s,
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si_i => si_s,
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si_i => si_s,
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so_o => so_s,
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so_o => so_s,
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sk_o => sk_s,
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sk_o => sk_s,
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io_l_b => io_l_s,
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io_l_b => io_l_s,
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io_d_o => io_d_s,
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io_d_o => io_d_s,
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io_g_b => io_g_s
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io_g_b => io_g_s
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);
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);
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io_l_s <= (others => 'H');
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io_l_s <= (others => 'H');
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io_d_s <= (others => 'H');
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io_d_s <= (others => 'H');
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io_g_s <= (others => 'H');
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io_g_s <= (others => 'H');
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Testbench elements
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-- Testbench elements
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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tb_elems_b : tb_elems
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tb_elems_b : tb_elems
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generic map (
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generic map (
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period_g => period_c,
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period_g => period_c,
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d_width_g => 2,
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d_width_g => 2,
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g_width_g => 3
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g_width_g => 3
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)
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)
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port map (
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port map (
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io_l_i => io_l_s,
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io_l_i => io_l_s,
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io_d_i => io_d_s,
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io_d_i => io_d_s,
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io_g_i => io_g_s,
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io_g_i => io_g_s,
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io_in_o => open,
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io_in_o => open,
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so_i => so_s,
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so_i => so_s,
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si_o => si_s,
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si_o => si_s,
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sk_i => sk_s,
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sk_i => sk_s,
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ck_o => ck_s
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ck_o => ck_s
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);
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);
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end behav;
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end behav;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.5 2006/05/27 19:10:12 arniml
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-- explicitly select clock divider 8
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--
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-- Revision 1.4 2006/05/23 01:18:26 arniml
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-- consider IN port
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--
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-- Revision 1.3 2006/05/15 21:56:02 arniml
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-- moved elements to separate design unit tb_elems
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--
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-- Revision 1.2 2006/05/06 13:34:25 arniml
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-- remove delta cycle filter on sk_s
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--
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-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
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-- import from local CVS repository, LOC_CVS_0_1
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--
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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