-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- $Id: t400_tech_comp_pack-p.vhd,v 1.2 2006-06-05 20:31:00 arniml Exp $
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-- $Id: t400_tech_comp_pack-p.vhd 179 2009-04-01 19:48:38Z arniml $
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--
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--
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-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package t400_tech_comp_pack is
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package t400_tech_comp_pack is
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component t400_por
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component t400_por
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generic (
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generic (
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delay_g : integer := 4;
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delay_g : integer := 4;
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cnt_width_g : integer := 2
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cnt_width_g : integer := 2
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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por_n_o : out std_logic
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por_n_o : out std_logic
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);
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);
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end component;
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end component;
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component generic_ram
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component generic_ram
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generic (
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generic (
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addr_width_g : integer := 10;
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addr_width_g : integer := 10;
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data_width_g : integer := 8
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data_width_g : integer := 8
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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we_i : in std_logic;
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we_i : in std_logic;
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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);
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end component;
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end component;
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component generic_ram_ena
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component generic_ram_ena
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generic (
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generic (
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addr_width_g : integer := 10;
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addr_width_g : integer := 10;
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data_width_g : integer := 8
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data_width_g : integer := 8
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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a_i : in std_logic_vector(addr_width_g-1 downto 0);
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we_i : in std_logic;
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we_i : in std_logic;
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ena_i : in std_logic;
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ena_i : in std_logic;
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_i : in std_logic_vector(data_width_g-1 downto 0);
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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d_o : out std_logic_vector(data_width_g-1 downto 0)
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);
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);
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end component;
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end component;
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end t400_tech_comp_pack;
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end t400_tech_comp_pack;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: not supported by cvs2svn $
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-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
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-- import from local CVS repository, LOC_CVS_0_1
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--
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-------------------------------------------------------------------------------
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No newline at end of file
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