-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
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--
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--
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-- The Arithmetic Logic Unit (ALU).
|
-- The Arithmetic Logic Unit (ALU).
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-- It contains the accumulator and the C flag.
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-- It contains the accumulator and the C flag.
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--
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--
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-- $Id: t400_alu.vhd,v 1.3 2006-05-22 00:01:56 arniml Exp $
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-- $Id: t400_alu.vhd 179 2009-04-01 19:48:38Z arniml $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t400/
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-- http://www.opencores.org/cvsweb.shtml/t400/
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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use work.t400_pack.all;
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use work.t400_pack.all;
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use work.t400_opt_pack.all;
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use work.t400_opt_pack.all;
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|
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entity t400_alu is
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entity t400_alu is
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|
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generic (
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generic (
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opt_cko_g : integer := t400_opt_cko_crystal_c
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opt_cko_g : integer := t400_opt_cko_crystal_c
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);
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);
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port (
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port (
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-- System Interface -------------------------------------------------------
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-- System Interface -------------------------------------------------------
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ck_i : in std_logic;
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ck_i : in std_logic;
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ck_en_i : in boolean;
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ck_en_i : in boolean;
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por_i : in boolean;
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por_i : in boolean;
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res_i : in boolean;
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res_i : in boolean;
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cko_i : in std_logic;
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cko_i : in std_logic;
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-- Control Interface ------------------------------------------------------
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-- Control Interface ------------------------------------------------------
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op_i : in alu_op_t;
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op_i : in alu_op_t;
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-- Data Interface ---------------------------------------------------------
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-- Data Interface ---------------------------------------------------------
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m_i : in dw_t;
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m_i : in dw_t;
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dec_data_i : in dec_data_t;
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dec_data_i : in dec_data_t;
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q_low_i : in dw_t;
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q_low_i : in dw_t;
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b_i : in b_t;
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b_i : in b_t;
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g_i : in dw_t;
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g_i : in dw_t;
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in_i : in dw_t;
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in_i : in dw_t;
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sio_i : in dw_t;
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sio_i : in dw_t;
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a_o : out dw_t;
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a_o : out dw_t;
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carry_o : out std_logic;
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carry_o : out std_logic;
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c_o : out std_logic
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c_o : out std_logic
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);
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);
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|
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end t400_alu;
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end t400_alu;
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library ieee;
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library ieee;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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|
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architecture rtl of t400_alu is
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architecture rtl of t400_alu is
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|
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subtype alu_dw_t is unsigned(dw_t'high+1 downto 0);
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subtype alu_dw_t is unsigned(dw_t'high+1 downto 0);
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signal alu_result_s : alu_dw_t;
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signal alu_result_s : alu_dw_t;
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|
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signal a_q : dw_t;
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signal a_q : dw_t;
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signal c_q : std_logic;
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signal c_q : std_logic;
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|
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begin
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begin
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process regs
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-- Process regs
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--
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--
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-- Purpose:
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-- Purpose:
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-- Implements the sequential registers of the ALU:
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-- Implements the sequential registers of the ALU:
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-- * A - accumulator
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-- * A - accumulator
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-- * C - carry flag
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-- * C - carry flag
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--
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--
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regs: process (ck_i, por_i)
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regs: process (ck_i, por_i)
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begin
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begin
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if por_i then
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if por_i then
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a_q <= (others => '0');
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a_q <= (others => '0');
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c_q <= '0';
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c_q <= '0';
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elsif ck_i'event and ck_i = '1' then
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elsif ck_i'event and ck_i = '1' then
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if res_i then
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if res_i then
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-- synchronous reset upon external reset event
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-- synchronous reset upon external reset event
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a_q <= (others => '0');
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a_q <= (others => '0');
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c_q <= '0';
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c_q <= '0';
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|
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elsif ck_en_i then
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elsif ck_en_i then
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-- update accumulator
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-- update accumulator
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case op_i is
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case op_i is
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when ALU_CLRA |
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when ALU_CLRA |
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ALU_ADD |
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ALU_ADD |
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ALU_ADD_10 |
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ALU_ADD_10 |
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ALU_ADD_C |
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ALU_ADD_C |
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ALU_ADD_DEC |
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ALU_ADD_DEC |
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ALU_COMP |
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ALU_COMP |
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ALU_XOR =>
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ALU_XOR =>
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a_q <= std_logic_vector(alu_result_s(dw_t'range));
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a_q <= std_logic_vector(alu_result_s(dw_t'range));
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when ALU_LOAD_M =>
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when ALU_LOAD_M =>
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a_q <= m_i;
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a_q <= m_i;
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when ALU_LOAD_Q =>
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when ALU_LOAD_Q =>
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a_q <= q_low_i;
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a_q <= q_low_i;
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when ALU_LOAD_G =>
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when ALU_LOAD_G =>
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a_q <= g_i;
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a_q <= g_i;
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when ALU_LOAD_IN =>
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when ALU_LOAD_IN =>
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a_q <= in_i;
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a_q <= in_i;
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when ALU_LOAD_IL =>
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when ALU_LOAD_IL =>
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a_q(3) <= in_i(3);
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a_q(3) <= in_i(3);
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if opt_cko_g = t400_opt_cko_gpi_c then
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if opt_cko_g = t400_opt_cko_gpi_c then
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a_q(2) <= cko_i;
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a_q(2) <= cko_i;
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else
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else
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a_q(2) <= '1';
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a_q(2) <= '1';
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end if;
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end if;
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a_q(1) <= '0';
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a_q(1) <= '0';
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a_q(0) <= in_i(0);
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a_q(0) <= in_i(0);
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when ALU_LOAD_BR =>
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when ALU_LOAD_BR =>
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a_q(3 downto 2) <= (others => '0');
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a_q(3 downto 2) <= (others => '0');
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a_q(1 downto 0) <= b_i(br_range_t);
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a_q(1 downto 0) <= b_i(br_range_t);
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when ALU_LOAD_BD =>
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when ALU_LOAD_BD =>
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a_q <= b_i(bd_range_t);
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a_q <= b_i(bd_range_t);
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when ALU_LOAD_SIO =>
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when ALU_LOAD_SIO =>
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a_q <= sio_i;
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a_q <= sio_i;
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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-- update C flag upon the following instructions
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-- update C flag upon the following instructions
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case op_i is
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case op_i is
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-- carry result of addition -----------------------------------------
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-- carry result of addition -----------------------------------------
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when ALU_ADD_C =>
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when ALU_ADD_C =>
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c_q <= alu_result_s(alu_dw_t'high);
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c_q <= alu_result_s(alu_dw_t'high);
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|
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-- reset C flag -----------------------------------------------------
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-- reset C flag -----------------------------------------------------
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when ALU_RC =>
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when ALU_RC =>
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c_q <= '0';
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c_q <= '0';
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|
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-- set C flag -------------------------------------------------------
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-- set C flag -------------------------------------------------------
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when ALU_SC =>
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when ALU_SC =>
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c_q <= '1';
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c_q <= '1';
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|
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process regs;
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end process regs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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|
|
|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process dp
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-- Process dp
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--
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--
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-- Purpose:
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-- Purpose:
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-- Implements the ALU's data path.
|
-- Implements the ALU's data path.
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--
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--
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dp: process (op_i,
|
dp: process (op_i,
|
a_q,
|
a_q,
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m_i,
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m_i,
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dec_data_i,
|
dec_data_i,
|
c_q)
|
c_q)
|
variable in1_v,
|
variable in1_v,
|
in2_v,
|
in2_v,
|
in3_v,
|
in3_v,
|
add_v, xor_v : alu_dw_t;
|
add_v, xor_v : alu_dw_t;
|
begin
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begin
|
-- prepare adder
|
-- prepare adder
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in1_v := '0' & unsigned(a_q);
|
in1_v := '0' & unsigned(a_q);
|
if op_i = ALU_ADD_10 then
|
if op_i = ALU_ADD_10 then
|
in2_v := to_unsigned(10, alu_dw_t'length);
|
in2_v := to_unsigned(10, alu_dw_t'length);
|
elsif op_i = ALU_ADD_DEC then
|
elsif op_i = ALU_ADD_DEC then
|
in2_v := '0' & unsigned(dec_data_i(dw_t'range));
|
in2_v := '0' & unsigned(dec_data_i(dw_t'range));
|
else
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else
|
in2_v := '0' & unsigned(m_i);
|
in2_v := '0' & unsigned(m_i);
|
end if;
|
end if;
|
if op_i = ALU_ADD_C then
|
if op_i = ALU_ADD_C then
|
in3_v := (others => '0');
|
in3_v := (others => '0');
|
in3_v(0) := c_q;
|
in3_v(0) := c_q;
|
else
|
else
|
in3_v := (others => '0');
|
in3_v := (others => '0');
|
end if;
|
end if;
|
add_v := in1_v + in2_v + in3_v;
|
add_v := in1_v + in2_v + in3_v;
|
|
|
-- prepare exclusive or
|
-- prepare exclusive or
|
xor_v := in1_v xor in2_v;
|
xor_v := in1_v xor in2_v;
|
|
|
case op_i is
|
case op_i is
|
-- ALU operation: Clear accumulator -------------------------------------
|
-- ALU operation: Clear accumulator -------------------------------------
|
when ALU_CLRA =>
|
when ALU_CLRA =>
|
alu_result_s <= (others => '0');
|
alu_result_s <= (others => '0');
|
|
|
-- ALU operation: Add to accumulator ------------------------------------
|
-- ALU operation: Add to accumulator ------------------------------------
|
when ALU_ADD |
|
when ALU_ADD |
|
ALU_ADD_10 |
|
ALU_ADD_10 |
|
ALU_ADD_C |
|
ALU_ADD_C |
|
ALU_ADD_DEC =>
|
ALU_ADD_DEC =>
|
alu_result_s <= add_v;
|
alu_result_s <= add_v;
|
|
|
-- ALU operation: Complement accumulator --------------------------------
|
-- ALU operation: Complement accumulator --------------------------------
|
when ALU_COMP =>
|
when ALU_COMP =>
|
alu_result_s <= '0' & not unsigned(a_q);
|
alu_result_s <= '0' & not unsigned(a_q);
|
|
|
-- ALU operation: XOR to accumulator ------------------------------------
|
-- ALU operation: XOR to accumulator ------------------------------------
|
when ALU_XOR =>
|
when ALU_XOR =>
|
alu_result_s <= xor_v;
|
alu_result_s <= xor_v;
|
|
|
when others =>
|
when others =>
|
alu_result_s <= (others => '-');
|
alu_result_s <= (others => '-');
|
end case;
|
end case;
|
end process dp;
|
end process dp;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output mapping
|
-- Output mapping
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
a_o <= a_q;
|
a_o <= a_q;
|
carry_o <= alu_result_s(alu_dw_t'high);
|
carry_o <= alu_result_s(alu_dw_t'high);
|
c_o <= c_q;
|
c_o <= c_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
|
-- File History:
|
|
--
|
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.2 2006/05/21 21:47:40 arniml
|
|
-- route cko to ALU for INIL instruction
|
|
--
|
|
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
|
|
-- import from local CVS repository, LOC_CVS_0_1
|
|
--
|
|
-------------------------------------------------------------------------------
|
|
|
|
No newline at end of file
|
No newline at end of file
|