-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- The reset generation unit.
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-- The reset generation unit.
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--
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--
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-- $Id: t400_reset.vhd,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
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-- $Id: t400_reset.vhd 179 2009-04-01 19:48:38Z arniml $
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--
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--
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t400/
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-- http://www.opencores.org/cvsweb.shtml/t400/
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity t400_reset is
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entity t400_reset is
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port (
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port (
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-- System Interface -------------------------------------------------------
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-- System Interface -------------------------------------------------------
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ck_i : in std_logic;
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ck_i : in std_logic;
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icyc_en_i : in boolean;
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icyc_en_i : in boolean;
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por_i : in boolean;
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por_i : in boolean;
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-- Reset Interface --------------------------------------------------------
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-- Reset Interface --------------------------------------------------------
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reset_n_i : in std_logic;
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reset_n_i : in std_logic;
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res_o : out boolean
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res_o : out boolean
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);
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);
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end t400_reset;
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end t400_reset;
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library ieee;
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library ieee;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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architecture rtl of t400_reset is
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architecture rtl of t400_reset is
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type res_state_t is (IDLE,
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type res_state_t is (IDLE,
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RES1, RES2,
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RES1, RES2,
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RES_ACTIVE);
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RES_ACTIVE);
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signal res_state_q : res_state_t;
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signal res_state_q : res_state_t;
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signal res_q : boolean;
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signal res_q : boolean;
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begin
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begin
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process res_fsm
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-- Process res_fsm
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--
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--
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-- Purpose:
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-- Purpose:
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-- Implements the reset timing/controlling FSM.
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-- Implements the reset timing/controlling FSM.
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-- User's Guide chapter 2.3 requires that reset_n_i has to be low for
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-- User's Guide chapter 2.3 requires that reset_n_i has to be low for
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-- at least 3 instruction cycle times until it initializes the CPU.
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-- at least 3 instruction cycle times until it initializes the CPU.
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--
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--
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res_fsm: process (ck_i, por_i)
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res_fsm: process (ck_i, por_i)
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begin
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begin
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if por_i then
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if por_i then
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res_state_q <= IDLE;
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res_state_q <= IDLE;
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res_q <= false;
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res_q <= false;
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elsif ck_i'event and ck_i = '1' then
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elsif ck_i'event and ck_i = '1' then
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res_q <= false;
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res_q <= false;
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if icyc_en_i then
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if icyc_en_i then
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case res_state_q is
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case res_state_q is
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when IDLE =>
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when IDLE =>
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if reset_n_i = '0' then
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if reset_n_i = '0' then
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res_state_q <= RES1;
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res_state_q <= RES1;
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end if;
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end if;
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when RES1 =>
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when RES1 =>
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if reset_n_i = '0' then
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if reset_n_i = '0' then
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res_state_q <= RES2;
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res_state_q <= RES2;
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else
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else
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res_state_q <= IDLE;
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res_state_q <= IDLE;
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end if;
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end if;
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when RES2 =>
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when RES2 =>
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if reset_n_i = '0' then
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if reset_n_i = '0' then
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res_state_q <= RES_ACTIVE;
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res_state_q <= RES_ACTIVE;
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else
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else
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res_state_q <= IDLE;
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res_state_q <= IDLE;
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end if;
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end if;
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when RES_ACTIVE =>
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when RES_ACTIVE =>
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res_q <= true;
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res_q <= true;
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if reset_n_i = '1' then
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if reset_n_i = '1' then
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res_state_q <= IDLE;
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res_state_q <= IDLE;
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end if;
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end if;
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when others =>
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when others =>
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res_state_q <= IDLE;
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res_state_q <= IDLE;
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end case;
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end case;
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end if;
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end if;
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end if;
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end if;
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end process res_fsm;
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end process res_fsm;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Output mapping
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-- Output mapping
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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res_o <= res_q;
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res_o <= res_q;
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end rtl;
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end rtl;
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-------------------------------------------------------------------------------
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|
-- File History:
|
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--
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|
-- $Log: not supported by cvs2svn $
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-------------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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