OpenCores
URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [sw/] [verif/] [black_box/] [inil/] [test.asm] - Diff between revs 176 and 179

Only display areas with differences | Details | Blame | View Log

Rev 176 Rev 179
        ;; *******************************************************************
        ;; *******************************************************************
        ;; $Id: test.asm,v 1.2 2006-05-24 00:48:04 arniml Exp $
        ;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
        ;;
        ;;
        ;; Checks the INIL instruction.
        ;; Checks the INIL instruction.
        ;;
        ;;
        ;; the cpu type is defined on asl's command line
        ;; the cpu type is defined on asl's command line
        org     0x00
        org     0x00
        clra
        clra
        ;; check reset level of latches
        ;; check reset level of latches
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jmp     fail
        jmp     fail
        skmbz   2               ; CKO
        skmbz   2               ; CKO
        jmp     fail
        jmp     fail
        skmbz   0
        skmbz   0
        jmp     fail
        jmp     fail
        ;; set IN to 0xf and recheck levels
        ;; set IN to 0xf and recheck levels
        ogi     0xf
        ogi     0xf
        nop
        nop
        nop
        nop
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jmp     fail
        jmp     fail
        skmbz   2               ; CKO
        skmbz   2               ; CKO
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+       skmbz   0
+       skmbz   0
        jmp     fail
        jmp     fail
        ;; set IN0 to 0 and check that IL0 triggered
        ;; set IN0 to 0 and check that IL0 triggered
        ogi     0xe
        ogi     0xe
        nop
        nop
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jmp     fail
        jmp     fail
        skmbz   2               ; CKO
        skmbz   2               ; CKO
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+       skmbz   0
+       skmbz   0
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+
+
        jmp     page_1
        jmp     page_1
        org     0x040
        org     0x040
page_1:
page_1:
        ;; set IN3 to 0 and check that IL1 triggered
        ;; set IN3 to 0 and check that IL1 triggered
        ogi     0x6
        ogi     0x6
        nop
        nop
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+       skmbz   2               ; CKO
+       skmbz   2               ; CKO
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+       skmbz   0
+       skmbz   0
        jmp     fail
        jmp     fail
        ;; reload IN3 to trigger both IL latches
        ;; reload IN3 to trigger both IL latches
        ogi     0x9
        ogi     0x9
        ogi     0x0
        ogi     0x0
        nop
        nop
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+       skmbz   2               ; CKO
+       skmbz   2               ; CKO
        jmp     fail
        jmp     fail
        skmbz   0
        skmbz   0
        jp      +
        jp      +
        jmp     fail
        jmp     fail
+
+
        ;; check that INIL prevents setting of IL latches
        ;; check that INIL prevents setting of IL latches
        ;; when both events occur at the same cycle
        ;; when both events occur at the same cycle
        ogi     0x9
        ogi     0x9
        ogi     0x0
        ogi     0x0
        inil
        inil
        x       0
        x       0
        skmbz   3
        skmbz   3
        jmp     fail
        jmp     fail
        skmbz   2               ; CKO
        skmbz   2               ; CKO
        jmp     fail
        jmp     fail
        skmbz   0
        skmbz   0
        jmp     fail
        jmp     fail
        jmp     pass
        jmp     pass
        org     0x100
        org     0x100
        include "pass_fail.asm"
        include "pass_fail.asm"
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.