URL
https://opencores.org/ocsvn/t400/t400/trunk
Only display areas with differences |
Details |
Blame |
View Log
| Rev 176 |
Rev 179 |
;; *******************************************************************
|
;; *******************************************************************
|
;; $Id: test.asm,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
|
;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
|
;;
|
;;
|
;; Checks the JSR instruction.
|
;; Checks the JSR instruction.
|
;;
|
;;
|
|
|
;; the cpu type is defined on asl's command line
|
;; the cpu type is defined on asl's command line
|
|
|
org 0x00
|
org 0x00
|
clra
|
clra
|
|
|
;; preload data memory with jsr target values
|
;; preload data memory with jsr target values
|
stii 0x0
|
stii 0x0
|
stii 0x1
|
stii 0x1
|
stii 0x2
|
stii 0x2
|
stii 0x3
|
stii 0x3
|
stii 0x4
|
stii 0x4
|
stii 0x5
|
stii 0x5
|
stii 0x6
|
stii 0x6
|
stii 0x7
|
stii 0x7
|
|
|
cab
|
cab
|
jsr target_0
|
jsr target_0
|
;;
|
;;
|
aisc 0x1
|
aisc 0x1
|
cab
|
cab
|
clra
|
clra
|
jsr target_1
|
jsr target_1
|
;;
|
;;
|
aisc 0x2
|
aisc 0x2
|
cab
|
cab
|
clra
|
clra
|
jsr target_2
|
jsr target_2
|
;;
|
;;
|
aisc 0x3
|
aisc 0x3
|
cab
|
cab
|
clra
|
clra
|
jsr target_3
|
jsr target_3
|
;;
|
;;
|
IF MOMCPUNAME <> "COP410"
|
IF MOMCPUNAME <> "COP410"
|
aisc 0x4
|
aisc 0x4
|
cab
|
cab
|
clra
|
clra
|
jsr target_4
|
jsr target_4
|
;;
|
;;
|
aisc 0x5
|
aisc 0x5
|
cab
|
cab
|
clra
|
clra
|
jsr target_5
|
jsr target_5
|
;;
|
;;
|
aisc 0x6
|
aisc 0x6
|
cab
|
cab
|
clra
|
clra
|
jsr target_6
|
jsr target_6
|
;;
|
;;
|
aisc 0x7
|
aisc 0x7
|
cab
|
cab
|
clra
|
clra
|
jsr target_7
|
jsr target_7
|
ENDIF
|
ENDIF
|
|
|
jmp pass
|
jmp pass
|
|
|
;; subroutine targets
|
;; subroutine targets
|
org 0x06f
|
org 0x06f
|
target_0:
|
target_0:
|
ske
|
ske
|
jmp fail
|
jmp fail
|
ret
|
ret
|
;;
|
;;
|
org 0x09e
|
org 0x09e
|
target_1:
|
target_1:
|
aisc 0x1
|
aisc 0x1
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
org 0x12d
|
org 0x12d
|
target_2:
|
target_2:
|
aisc 0x2
|
aisc 0x2
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
org 0x13c
|
org 0x13c
|
target_3:
|
target_3:
|
aisc 0x3
|
aisc 0x3
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
IF MOMCPUNAME <> "COP410"
|
IF MOMCPUNAME <> "COP410"
|
org 0x24b
|
org 0x24b
|
target_4:
|
target_4:
|
aisc 0x4
|
aisc 0x4
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
org 0x2da
|
org 0x2da
|
target_5:
|
target_5:
|
aisc 0x5
|
aisc 0x5
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
org 0x369
|
org 0x369
|
target_6:
|
target_6:
|
aisc 0x6
|
aisc 0x6
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
;;
|
;;
|
org 0x378
|
org 0x378
|
target_7:
|
target_7:
|
aisc 0x7
|
aisc 0x7
|
ske
|
ske
|
jmp fail
|
jmp fail
|
clra
|
clra
|
ret
|
ret
|
ENDIF
|
ENDIF
|
|
|
org 0x1d0
|
org 0x1d0
|
include "pass_fail.asm"
|
include "pass_fail.asm"
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.