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Rev 179 |
;; *******************************************************************
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;; *******************************************************************
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;; $Id: test.asm,v 1.1.1.1 2006-05-06 01:56:45 arniml Exp $
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;; $Id: test.asm 179 2009-04-01 19:48:38Z arniml $
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;;
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;;
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;; Checks the LBI instruction (single byte).
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;; Checks the LBI instruction (single byte).
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;;
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;;
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;; the cpu type is defined on asl's command line
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;; the cpu type is defined on asl's command line
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org 0x00
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org 0x00
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clra
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clra
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;;
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;;
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;; initialize 4 x 8 RAM digits
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;; initialize 4 x 8 RAM digits
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;;
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;;
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;; register 0
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;; register 0
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stii 0x0
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stii 0x0
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aisc 0x9
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aisc 0x9
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cab
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cab
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stii 0x1
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stii 0x1
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stii 0x2
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stii 0x2
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stii 0x3
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stii 0x3
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stii 0x4
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stii 0x4
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stii 0x5
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stii 0x5
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stii 0x6
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stii 0x6
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stii 0x7
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stii 0x7
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;; register 1
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;; register 1
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ld 0x1
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ld 0x1
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stii 0x4
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stii 0x4
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cba
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cba
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aisc 0x8
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aisc 0x8
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cab
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cab
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stii 0x5
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stii 0x5
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stii 0x6
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stii 0x6
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stii 0x7
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stii 0x7
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stii 0x8
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stii 0x8
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stii 0x9
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stii 0x9
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stii 0xa
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stii 0xa
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stii 0xb
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stii 0xb
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;; register 2
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;; register 2
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ld 0x3
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ld 0x3
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stii 0x8
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stii 0x8
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cba
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cba
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aisc 0x8
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aisc 0x8
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cab
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cab
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stii 0x9
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stii 0x9
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stii 0xa
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stii 0xa
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stii 0xb
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stii 0xb
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stii 0xc
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stii 0xc
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stii 0xd
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stii 0xd
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stii 0xe
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stii 0xe
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stii 0xf
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stii 0xf
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;; register 3
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;; register 3
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ld 0x1
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ld 0x1
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stii 0xc
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stii 0xc
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cba
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cba
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aisc 0x8
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aisc 0x8
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cab
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cab
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stii 0xd
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stii 0xd
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stii 0xe
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stii 0xe
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stii 0xf
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stii 0xf
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stii 0x0
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stii 0x0
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stii 0x1
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stii 0x1
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stii 0x2
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stii 0x2
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stii 0x3
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stii 0x3
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jmp test_code
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jmp test_code
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;; subroutine page 2
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;; subroutine page 2
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org 0x80
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org 0x80
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lbi_call_reg0:
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lbi_call_reg0:
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lbi 0, 0
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lbi 0, 0
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lbi 0, 9
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lbi 0, 9
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lbi 0, 10
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lbi 0, 10
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lbi 0, 11
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lbi 0, 11
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lbi 0, 12
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lbi 0, 12
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lbi 0, 13
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lbi 0, 13
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lbi 0, 14
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lbi 0, 14
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lbi 0, 15
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lbi 0, 15
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ret
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ret
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lbi_call_reg1:
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lbi_call_reg1:
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lbi 1, 0
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lbi 1, 0
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lbi 1, 9
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lbi 1, 9
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lbi 1, 10
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lbi 1, 10
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lbi 1, 11
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lbi 1, 11
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lbi 1, 12
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lbi 1, 12
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lbi 1, 13
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lbi 1, 13
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lbi 1, 14
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lbi 1, 14
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lbi 1, 15
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lbi 1, 15
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ret
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ret
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lbi_call_reg2:
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lbi_call_reg2:
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lbi 2, 0
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lbi 2, 0
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lbi 2, 9
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lbi 2, 9
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lbi 2, 10
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lbi 2, 10
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lbi 2, 11
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lbi 2, 11
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lbi 2, 12
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lbi 2, 12
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lbi 2, 13
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lbi 2, 13
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lbi 2, 14
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lbi 2, 14
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lbi 2, 15
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lbi 2, 15
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ret
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ret
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lbi_call_reg3:
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lbi_call_reg3:
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lbi 3, 0
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lbi 3, 0
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lbi 3, 9
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lbi 3, 9
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lbi 3, 10
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lbi 3, 10
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lbi 3, 11
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lbi 3, 11
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lbi 3, 12
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lbi 3, 12
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lbi 3, 13
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lbi 3, 13
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lbi 3, 14
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lbi 3, 14
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lbi 3, 15
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lbi 3, 15
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ret
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ret
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org 0x100
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org 0x100
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;;
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;;
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;; now test each register digit
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;; now test each register digit
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;;
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;;
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test_code:
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test_code:
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;; register 0
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;; register 0
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;; digit 0
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;; digit 0
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clra
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clra
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jsrp lbi_call_reg0 + 0
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jsrp lbi_call_reg0 + 0
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ske
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ske
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jmp fail
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jmp fail
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;; digit 9
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;; digit 9
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 1
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jsrp lbi_call_reg0 + 1
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ske
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ske
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jmp fail
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jmp fail
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;; digit 10
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;; digit 10
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 2
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jsrp lbi_call_reg0 + 2
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ske
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ske
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jmp fail
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jmp fail
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;; digit 11
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;; digit 11
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 3
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jsrp lbi_call_reg0 + 3
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ske
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ske
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jmp fail
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jmp fail
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;; digit 12
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;; digit 12
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 4
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jsrp lbi_call_reg0 + 4
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ske
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ske
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jmp fail
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jmp fail
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;; digit 13
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;; digit 13
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 5
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jsrp lbi_call_reg0 + 5
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ske
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ske
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jmp fail
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jmp fail
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;; digit 14
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;; digit 14
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 6
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jsrp lbi_call_reg0 + 6
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ske
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ske
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jmp fail
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jmp fail
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;; digit 15
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;; digit 15
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg0 + 7
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jsrp lbi_call_reg0 + 7
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ske
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ske
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jmp fail
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jmp fail
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;; register 1
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;; register 1
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;; digit 0
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;; digit 0
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clra
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clra
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aisc 0x4
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aisc 0x4
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jsrp lbi_call_reg1 + 0
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jsrp lbi_call_reg1 + 0
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ske
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ske
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jmp fail
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jmp fail
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;; digit 9
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;; digit 9
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 1
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jsrp lbi_call_reg1 + 1
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ske
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ske
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jmp fail
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jmp fail
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;; digit 10
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;; digit 10
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 2
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jsrp lbi_call_reg1 + 2
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ske
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ske
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jmp fail
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jmp fail
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;; digit 11
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;; digit 11
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 3
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jsrp lbi_call_reg1 + 3
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ske
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ske
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jmp fail
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jmp fail
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;; digit 12
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;; digit 12
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 4
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jsrp lbi_call_reg1 + 4
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ske
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ske
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jmp fail
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jmp fail
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;; digit 13
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;; digit 13
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 5
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jsrp lbi_call_reg1 + 5
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ske
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ske
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jmp fail
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jmp fail
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;; digit 14
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;; digit 14
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 6
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jsrp lbi_call_reg1 + 6
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ske
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ske
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jmp fail
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jmp fail
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;; digit 15
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;; digit 15
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg1 + 7
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jsrp lbi_call_reg1 + 7
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ske
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ske
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jmp fail
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jmp fail
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;; register 2
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;; register 2
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;; digit 0
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;; digit 0
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clra
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clra
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aisc 0x8
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aisc 0x8
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jsrp lbi_call_reg2 + 0
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jsrp lbi_call_reg2 + 0
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ske
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ske
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jmp fail
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jmp fail
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;; digit 9
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;; digit 9
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 1
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jsrp lbi_call_reg2 + 1
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ske
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ske
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jmp fail
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jmp fail
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;; digit 10
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;; digit 10
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 2
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jsrp lbi_call_reg2 + 2
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ske
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ske
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jmp fail
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jmp fail
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;; digit 11
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;; digit 11
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 3
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jsrp lbi_call_reg2 + 3
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ske
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ske
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jmp fail
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jmp fail
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;; digit 12
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;; digit 12
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 4
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jsrp lbi_call_reg2 + 4
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ske
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ske
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jmp fail
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jmp fail
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;; digit 13
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;; digit 13
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 5
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jsrp lbi_call_reg2 + 5
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ske
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ske
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jmp fail
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jmp fail
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;; digit 14
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;; digit 14
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 6
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jsrp lbi_call_reg2 + 6
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ske
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ske
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jmp fail
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jmp fail
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;; digit 15
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;; digit 15
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg2 + 7
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jsrp lbi_call_reg2 + 7
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ske
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ske
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jmp fail
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jmp fail
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;; register 3
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;; register 3
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;; digit 0
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;; digit 0
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clra
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clra
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aisc 0xc
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aisc 0xc
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jsrp lbi_call_reg3 + 0
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jsrp lbi_call_reg3 + 0
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ske
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ske
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jmp fail
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jmp fail
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;; digit 9
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;; digit 9
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 1
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jsrp lbi_call_reg3 + 1
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ske
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ske
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jmp fail
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jmp fail
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;; digit 10
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;; digit 10
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 2
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jsrp lbi_call_reg3 + 2
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ske
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ske
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jmp fail
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jmp fail
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;; digit 11
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;; digit 11
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 3
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jsrp lbi_call_reg3 + 3
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ske
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ske
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jmp fail
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jmp fail
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;; digit 12
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;; digit 12
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aisc 0x1
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aisc 0x1
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nop
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nop
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jsrp lbi_call_reg3 + 4
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jsrp lbi_call_reg3 + 4
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ske
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ske
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jmp fail
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jmp fail
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;; digit 13
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;; digit 13
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 5
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jsrp lbi_call_reg3 + 5
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ske
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ske
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jmp fail
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jmp fail
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;; digit 14
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;; digit 14
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 6
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jsrp lbi_call_reg3 + 6
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ske
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ske
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jmp fail
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jmp fail
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;; digit 15
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;; digit 15
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aisc 0x1
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aisc 0x1
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jsrp lbi_call_reg3 + 7
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jsrp lbi_call_reg3 + 7
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ske
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ske
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jmp fail
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jmp fail
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jmp pass
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jmp pass
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include "pass_fail.asm"
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include "pass_fail.asm"
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