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Known bugs of the T48 uController core
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Known bugs of the T48 uController core
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======================================
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======================================
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Version: $Date: 2006-07-14 01:06:36 $
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Version: $Date: 2006-07-14 01:06:36 $
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Release 0.6.1 BETA
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Release 0.6.1 BETA
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------------------
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------------------
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*******************************************************************************
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*******************************************************************************
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Deassertion of PROG too early
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Deassertion of PROG too early
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PROG is deasserted in XTAL2 cycle which might lead to read data being already
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PROG is deasserted in XTAL2 cycle which might lead to read data being already
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invalid (tri-stated) when the core samples P2[3:0] at the end of XTAL3.
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invalid (tri-stated) when the core samples P2[3:0] at the end of XTAL3.
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Fixed in:
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Fixed in:
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clock_ctrl.vhd 1.12
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clock_ctrl.vhd 1.12
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.6 BETA
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Release 0.6 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Deassertion of PROG too early
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Deassertion of PROG too early
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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After access to expander interface (ANLD Pp; MOVD A,Pp; MOVD Pp,A; ORLD Pp)
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After access to expander interface (ANLD Pp; MOVD A,Pp; MOVD Pp,A; ORLD Pp)
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the port value of P2 is restored. This is wrong according to chapter "Port 2
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the port value of P2 is restored. This is wrong according to chapter "Port 2
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Operations" of the "Expanded MCS-48 System" manual. It states that previously
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Operations" of the "Expanded MCS-48 System" manual. It states that previously
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latched I/O information will be removed and not restored.
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latched I/O information will be removed and not restored.
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Fixed in:
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Fixed in:
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p2.vhd 1.8
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p2.vhd 1.8
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Fix will be included in next release.
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Fix will be included in next release.
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*******************************************************************************
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*******************************************************************************
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Problem when INT and JMP
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Problem when INT and JMP
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When code is executed from Memory Bank 1, the injected CALL triggered by the
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When code is executed from Memory Bank 1, the injected CALL triggered by the
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interrupt does not always vector to address 3. This happens because of a bus
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interrupt does not always vector to address 3. This happens because of a bus
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collision between the decoder unit and the db_bus unit. The resulting address
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collision between the decoder unit and the db_bus unit. The resulting address
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can be either:
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can be either:
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* 000h, 001h, 002h, 003h for external and timer interrupt
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* 000h, 001h, 002h, 003h for external and timer interrupt
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* 004h, 005h, 006h, 007h for timer interrupt
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* 004h, 005h, 006h, 007h for timer interrupt
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The problem was introduced in release 0.6 BETA when the glitch on PCH was
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The problem was introduced in release 0.6 BETA when the glitch on PCH was
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fixed.
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fixed.
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Fixed in:
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Fixed in:
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decoder.vhd 1.21
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decoder.vhd 1.21
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New regression test: int_on_mb1
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New regression test: int_on_mb1
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.5 BETA
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Release 0.5 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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Deassertion of PROG too early
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Deassertion of PROG too early
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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An interrupt occuring during the execution of a JMP instruction, forces bit 11
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An interrupt occuring during the execution of a JMP instruction, forces bit 11
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of the target address to 0. This corrupts target addresses that are located in
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of the target address to 0. This corrupts target addresses that are located in
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Program Memory Bank 1.
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Program Memory Bank 1.
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Fixed in:
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Fixed in:
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int.vhd 1.5
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int.vhd 1.5
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New regression test: white_box/int_on_int
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New regression test: white_box/int_on_int
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Fix will be included in next release.
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Fix will be included in next release.
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*******************************************************************************
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*******************************************************************************
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MSB of Program Counter changed upon PC increment
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MSB of Program Counter changed upon PC increment
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The current implementation of the Program Counter allows that the MSB (bit 11)
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The current implementation of the Program Counter allows that the MSB (bit 11)
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is modifed when the PC increments at address 07FFh linear code execution. This
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is modifed when the PC increments at address 07FFh linear code execution. This
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is contrary to the description found in "The Expanded MCS-48 System" which
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is contrary to the description found in "The Expanded MCS-48 System" which
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states that bit 11 is only altered by JMP and CALL/RET but not by normal
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states that bit 11 is only altered by JMP and CALL/RET but not by normal
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increment.
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increment.
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Fixed in:
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Fixed in:
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pmem_crtl.vhd 1.4
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pmem_crtl.vhd 1.4
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New regression test: white_box/pc_wrap_bit11
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New regression test: white_box/pc_wrap_bit11
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Fix will be included in next release.
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Fix will be included in next release.
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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Wrong clock applied to T0
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After executing the 'ENT0 CLK' instruction, the internal clock (XTAL divided
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After executing the 'ENT0 CLK' instruction, the internal clock (XTAL divided
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by 3) should be applied to T0.
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by 3) should be applied to T0.
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The t48_core applies clk_i to T0. This is equal to XTAL in the current
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The t48_core applies clk_i to T0. This is equal to XTAL in the current
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implementation of t8048 and others. Therefore, the clock at T0 is three times
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implementation of t8048 and others. Therefore, the clock at T0 is three times
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faster than specified.
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faster than specified.
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Fixed in:
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Fixed in:
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clock_ctrl.vhd 1.7
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clock_ctrl.vhd 1.7
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t48_core.vhd 1.8
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t48_core.vhd 1.8
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.4 BETA
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Release 0.4 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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MSB of Program Counter changed upon PC increment
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MSB of Program Counter changed upon PC increment
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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Wrong clock applied to T0
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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The control signals RD' and WR' are not asserted when the instructions INS A,
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The control signals RD' and WR' are not asserted when the instructions INS A,
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BUS and OUTL BUS, A are executed. The BUS is read or written but the control
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BUS and OUTL BUS, A are executed. The BUS is read or written but the control
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signals are missing.
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signals are missing.
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Fixed in:
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Fixed in:
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decoder.vhd 1.16
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decoder.vhd 1.16
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Fix will be included in next release.
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Fix will be included in next release.
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*******************************************************************************
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*******************************************************************************
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P1 constantly in push-pull mode in t8048
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P1 constantly in push-pull mode in t8048
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Port P1 is constantly driven by an active push-pull driver instead of an
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Port P1 is constantly driven by an active push-pull driver instead of an
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open-collector driver type. This inhibits using any bit of P1 in input
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open-collector driver type. This inhibits using any bit of P1 in input
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direction.
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direction.
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Fixed in:
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Fixed in:
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t8048.vhd 1.4
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t8048.vhd 1.4
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.3 BETA
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Release 0.3 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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MSB of Program Counter changed upon PC increment
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MSB of Program Counter changed upon PC increment
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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Wrong clock applied to T0
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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P1 constantly in push-pull mode in t8048
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P1 constantly in push-pull mode in t8048
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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PSENn Timing
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PSENn Timing
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PSENn is erroneously activated during read or write from external memory when
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PSENn is erroneously activated during read or write from external memory when
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the read and write strobe signals RDn and WRn are active. This happens when
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the read and write strobe signals RDn and WRn are active. This happens when
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code is executed from external Program Memory.
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code is executed from external Program Memory.
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The problem lies in the decoder module where the PSENn signal is generated
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The problem lies in the decoder module where the PSENn signal is generated
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based on the current machine cycle.
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based on the current machine cycle.
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Fixed in decoder.vhd 1.15
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Fixed in decoder.vhd 1.15
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Added waveform check for PSENn in if_timing.vhd 1.3
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Added waveform check for PSENn in if_timing.vhd 1.3
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New regression test: white_box/psen_rd_wr_timing
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New regression test: white_box/psen_rd_wr_timing
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.2 BETA
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Release 0.2 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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MSB of Program Counter changed upon PC increment
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MSB of Program Counter changed upon PC increment
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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Wrong clock applied to T0
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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P1 constantly in push-pull mode in t8048
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P1 constantly in push-pull mode in t8048
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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PSENn Timing
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PSENn Timing
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Program Memory bank can be switched during interrupt
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Program Memory bank can be switched during interrupt
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During an interrupt service routine (i.e. after vectoring to location 3 or 7
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During an interrupt service routine (i.e. after vectoring to location 3 or 7
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of the Program Memory and befor executing the RETR instruction) the Program
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of the Program Memory and befor executing the RETR instruction) the Program
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Memory bank can be switched by executing a JMP or CALL instruction. These
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Memory bank can be switched by executing a JMP or CALL instruction. These
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instructions honour the current state of the Program Memory Bank Flag and thus
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instructions honour the current state of the Program Memory Bank Flag and thus
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switch the Program Memory bank upon execution.
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switch the Program Memory bank upon execution.
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Fixed in:
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Fixed in:
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int.vhd 1.2
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int.vhd 1.2
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decoder.vhd 1.14
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decoder.vhd 1.14
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Updated regression test:
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Updated regression test:
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black_box/mb/int
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black_box/mb/int
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Fix will be included in next release.
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Fix will be included in next release.
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Release 0.1 BETA
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Release 0.1 BETA
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----------------
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----------------
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*******************************************************************************
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*******************************************************************************
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P2 Port value restored after expander access
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P2 Port value restored after expander access
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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MSB of Program Counter changed upon PC increment
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MSB of Program Counter changed upon PC increment
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Wrong clock applied to T0
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Wrong clock applied to T0
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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PSENn Timing
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PSENn Timing
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See above.
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See above.
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*******************************************************************************
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*******************************************************************************
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Program Memory bank can be switched during interrupt
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Program Memory bank can be switched during interrupt
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See above.
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See above.
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******************************************************************************
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******************************************************************************
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External Program Memory ignored when EA = 0
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External Program Memory ignored when EA = 0
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The external Program Memory is always ignored when EA = 0 with the t8048 system
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The external Program Memory is always ignored when EA = 0 with the t8048 system
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toplevel. Desired behaviour is to access external Program Memory when code
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toplevel. Desired behaviour is to access external Program Memory when code
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has to be fetched from an address location that is outside the internal
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has to be fetched from an address location that is outside the internal
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Program Memory.
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Program Memory.
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Fixed in t8048.vhd 1.3
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Fixed in t8048.vhd 1.3
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Fix will be included in next release.
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Fix will be included in next release.
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******************************************************************************
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******************************************************************************
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ANL and ORL to P2 read port status instead of port output register
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ANL and ORL to P2 read port status instead of port output register
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The ANL and ORL instructions for P2 read the port status and apply the logical
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The ANL and ORL instructions for P2 read the port status and apply the logical
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operation on this value. Instead, they should read the port output register
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operation on this value. Instead, they should read the port output register
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and operate on this value.
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and operate on this value.
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Fixed in p2.vhd 1.5
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Fixed in p2.vhd 1.5
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Regression test:
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Regression test:
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white_box/p2_port_reg_conflict
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white_box/p2_port_reg_conflict
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Fix will be included in next release.
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Fix will be included in next release.
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******************************************************************************
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******************************************************************************
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Counter is not incremented
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Counter is not incremented
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When in counter mode, the timer/counter module does not increment upon a
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When in counter mode, the timer/counter module does not increment upon a
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falling edge of T1. Reason is a typo in the code for the edge detection signal
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falling edge of T1. Reason is a typo in the code for the edge detection signal
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t1_inc_s - it will never become true.
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t1_inc_s - it will never become true.
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Fixed in timer.vhd 1.3
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Fixed in timer.vhd 1.3
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Regression tests:
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Regression tests:
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black_box/cnt/cnt
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black_box/cnt/cnt
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black_box/cnt/int
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black_box/cnt/int
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Fix will be included in next release.
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Fix will be included in next release.
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