-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- T8039 Microcontroller System
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-- T8039 Microcontroller System
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--
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--
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-- $Id: t8039.vhd,v 1.2 2004-05-20 21:53:42 arniml Exp $
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-- $Id: t8039.vhd,v 1.2 2004-05-20 21:53:42 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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-- this list of conditions and the following disclaimer.
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--
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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-- documentation and/or other materials provided with the distribution.
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--
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--
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-- Neither the name of the author nor the names of other contributors may
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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-- specific prior written permission.
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--
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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--
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-- Please report bugs to the author, but before you do so, please
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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-- you have the latest version of this file.
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--
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--
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-- The latest version of this file can be found at:
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity t8039 is
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entity t8039 is
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port (
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port (
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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reset_n_i : in std_logic;
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reset_n_i : in std_logic;
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t0_b : inout std_logic;
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t0_b : inout std_logic;
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int_n_i : in std_logic;
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int_n_i : in std_logic;
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ea_i : in std_logic;
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ea_i : in std_logic;
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rd_n_o : out std_logic;
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rd_n_o : out std_logic;
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psen_n_o : out std_logic;
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psen_n_o : out std_logic;
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wr_n_o : out std_logic;
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wr_n_o : out std_logic;
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ale_o : out std_logic;
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ale_o : out std_logic;
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db_b : inout std_logic_vector( 7 downto 0);
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db_b : inout std_logic_vector( 7 downto 0);
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t1_i : in std_logic;
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t1_i : in std_logic;
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p2_b : inout std_logic_vector( 7 downto 0);
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p2_b : inout std_logic_vector( 7 downto 0);
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p1_b : inout std_logic_vector( 7 downto 0);
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p1_b : inout std_logic_vector( 7 downto 0);
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prog_n_o : out std_logic
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prog_n_o : out std_logic
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);
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);
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end t8039;
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end t8039;
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use work.t48_core_comp_pack.t48_core;
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use work.t48_core_comp_pack.t48_core;
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use work.t48_core_comp_pack.syn_rom;
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use work.t48_core_comp_pack.syn_rom;
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use work.t48_core_comp_pack.syn_ram;
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use work.t48_core_comp_pack.syn_ram;
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architecture struct of t8039 is
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architecture struct of t8039 is
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signal t0_s : std_logic;
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signal t0_s : std_logic;
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signal t0_dir_s : std_logic;
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signal t0_dir_s : std_logic;
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signal db_s : std_logic_vector( 7 downto 0);
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signal db_s : std_logic_vector( 7 downto 0);
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signal db_dir_s : std_logic;
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signal db_dir_s : std_logic;
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signal p2_s : std_logic_vector( 7 downto 0);
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signal p2_s : std_logic_vector( 7 downto 0);
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signal p2_low_imp_s : std_logic;
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signal p2_low_imp_s : std_logic;
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signal p1_s : std_logic_vector( 7 downto 0);
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signal p1_s : std_logic_vector( 7 downto 0);
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signal p1_low_imp_s : std_logic;
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signal p1_low_imp_s : std_logic;
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signal xtal3_s : std_logic;
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signal xtal3_s : std_logic;
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signal dmem_addr_s : std_logic_vector( 7 downto 0);
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signal dmem_addr_s : std_logic_vector( 7 downto 0);
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signal dmem_we_s : std_logic;
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signal dmem_we_s : std_logic;
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signal dmem_data_from_s : std_logic_vector( 7 downto 0);
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signal dmem_data_from_s : std_logic_vector( 7 downto 0);
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signal dmem_data_to_s : std_logic_vector( 7 downto 0);
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signal dmem_data_to_s : std_logic_vector( 7 downto 0);
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signal pmem_data_s : std_logic_vector( 7 downto 0);
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signal pmem_data_s : std_logic_vector( 7 downto 0);
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signal vdd_s : std_logic;
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signal vdd_s : std_logic;
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begin
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begin
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-- no Program memory available
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-- no Program memory available
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pmem_data_s <= (others => '0');
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pmem_data_s <= (others => '0');
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vdd_s <= '1';
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vdd_s <= '1';
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t48_core_b : t48_core
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t48_core_b : t48_core
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generic map (
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generic map (
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xtal_div_3_g => 1,
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xtal_div_3_g => 1,
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register_mnemonic_g => 1,
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register_mnemonic_g => 1,
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include_port1_g => 1,
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include_port1_g => 1,
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include_port2_g => 1,
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include_port2_g => 1,
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include_bus_g => 1,
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include_bus_g => 1,
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include_timer_g => 1,
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include_timer_g => 1,
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sample_t1_state_g => 4
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sample_t1_state_g => 4
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)
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)
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port map (
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port map (
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xtal_i => xtal_i,
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xtal_i => xtal_i,
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reset_i => reset_n_i,
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reset_i => reset_n_i,
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t0_i => t0_b,
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t0_i => t0_b,
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t0_o => t0_s,
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t0_o => t0_s,
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t0_dir_o => t0_dir_s,
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t0_dir_o => t0_dir_s,
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int_n_i => int_n_i,
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int_n_i => int_n_i,
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ea_i => vdd_s,
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ea_i => vdd_s,
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rd_n_o => rd_n_o,
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rd_n_o => rd_n_o,
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psen_n_o => psen_n_o,
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psen_n_o => psen_n_o,
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wr_n_o => wr_n_o,
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wr_n_o => wr_n_o,
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ale_o => ale_o,
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ale_o => ale_o,
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db_i => db_b,
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db_i => db_b,
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db_o => db_s,
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db_o => db_s,
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db_dir_o => db_dir_s,
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db_dir_o => db_dir_s,
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t1_i => t1_i,
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t1_i => t1_i,
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p2_i => p2_b,
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p2_i => p2_b,
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p2_o => p2_s,
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p2_o => p2_s,
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p2_low_imp_o => p2_low_imp_s,
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p2_low_imp_o => p2_low_imp_s,
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p1_i => p1_b,
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p1_i => p1_b,
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p1_o => p1_s,
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p1_o => p1_s,
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p1_low_imp_o => p1_low_imp_s,
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p1_low_imp_o => p1_low_imp_s,
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prog_n_o => prog_n_o,
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prog_n_o => prog_n_o,
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clk_i => xtal_i,
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clk_i => xtal_i,
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en_clk_i => xtal3_s,
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en_clk_i => xtal3_s,
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xtal3_o => xtal3_s,
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xtal3_o => xtal3_s,
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dmem_addr_o => dmem_addr_s,
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dmem_addr_o => dmem_addr_s,
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dmem_we_o => dmem_we_s,
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dmem_we_o => dmem_we_s,
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dmem_data_i => dmem_data_from_s,
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dmem_data_i => dmem_data_from_s,
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dmem_data_o => dmem_data_to_s,
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dmem_data_o => dmem_data_to_s,
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pmem_addr_o => open,
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pmem_addr_o => open,
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pmem_data_i => pmem_data_s
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pmem_data_i => pmem_data_s
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);
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);
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process bidirs
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-- Process bidirs
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--
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--
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-- Purpose:
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-- Purpose:
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-- Assign bidirectional signals.
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-- Assign bidirectional signals.
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--
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--
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bidirs: process (t0_b, t0_s, t0_dir_s,
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bidirs: process (t0_b, t0_s, t0_dir_s,
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db_b, db_s, db_dir_s,
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db_b, db_s, db_dir_s,
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p1_b, p1_s, p1_low_imp_s,
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p1_b, p1_s, p1_low_imp_s,
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p2_b, p2_s, p2_low_imp_s)
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p2_b, p2_s, p2_low_imp_s)
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function open_collector_f(sig : std_logic) return std_logic is
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function open_collector_f(sig : std_logic) return std_logic is
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variable sig_v : std_logic;
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variable sig_v : std_logic;
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begin
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begin
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sig_v := 'Z';
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sig_v := 'Z';
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if sig = '0' then
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if sig = '0' then
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sig_v := '0';
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sig_v := '0';
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end if;
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end if;
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return sig_v;
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return sig_v;
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end;
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end;
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begin
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begin
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-- Test 0 -----------------------------------------------------------------
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-- Test 0 -----------------------------------------------------------------
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if t0_dir_s = '1' then
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if t0_dir_s = '1' then
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t0_b <= t0_s;
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t0_b <= t0_s;
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else
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else
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t0_b <= 'Z';
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t0_b <= 'Z';
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end if;
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end if;
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-- Data Bus ---------------------------------------------------------------
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-- Data Bus ---------------------------------------------------------------
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if db_dir_s = '1' then
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if db_dir_s = '1' then
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db_b <= db_s;
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db_b <= db_s;
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else
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else
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db_b <= (others => 'Z');
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db_b <= (others => 'Z');
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end if;
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end if;
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-- Port 1 -----------------------------------------------------------------
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-- Port 1 -----------------------------------------------------------------
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for i in p1_b'range loop
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for i in p1_b'range loop
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p1_b(i) <= open_collector_f(p1_s(i));
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p1_b(i) <= open_collector_f(p1_s(i));
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end loop;
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end loop;
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-- if p1_low_imp_s = '1' then
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-- if p1_low_imp_s = '1' then
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-- p1_b <= p1_s;
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-- p1_b <= p1_s;
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-- else
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-- else
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-- p1_b <= (others => 'Z');
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-- p1_b <= (others => 'Z');
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-- end if;
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-- end if;
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-- Port 2 -----------------------------------------------------------------
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-- Port 2 -----------------------------------------------------------------
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for i in p2_b'range loop
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for i in p2_b'range loop
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p2_b(i) <= open_collector_f(p2_s(i));
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p2_b(i) <= open_collector_f(p2_s(i));
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end loop;
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end loop;
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-- if p2_low_imp_s = '1' then
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-- if p2_low_imp_s = '1' then
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-- p2_b <= p2_b_s;
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-- p2_b <= p2_b_s;
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-- else
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-- else
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-- p2_b <= (others => 'Z');
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-- p2_b <= (others => 'Z');
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-- end if;
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-- end if;
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end process bidirs;
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end process bidirs;
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--
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--
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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ram_128_b : syn_ram
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ram_128_b : syn_ram
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generic map (
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generic map (
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address_width_g => 7
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address_width_g => 7
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)
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)
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port map (
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port map (
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clk_i => xtal_i,
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clk_i => xtal_i,
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res_i => reset_n_i,
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res_i => reset_n_i,
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ram_addr_i => dmem_addr_s(6 downto 0),
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ram_addr_i => dmem_addr_s(6 downto 0),
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ram_data_i => dmem_data_to_s,
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ram_data_i => dmem_data_to_s,
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ram_we_i => dmem_we_s,
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ram_we_i => dmem_we_s,
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ram_data_o => dmem_data_from_s
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ram_data_o => dmem_data_from_s
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);
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);
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end struct;
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end struct;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
|
-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
|
-- Revision 1.1 2004/04/18 18:51:10 arniml
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-- Revision 1.1 2004/04/18 18:51:10 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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