-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $
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-- $Id: t48_core_comp_pack-p.vhd,v 1.2 2004-03-29 19:39:58 arniml Exp $
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--
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
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-- All rights reserved
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package t48_core_comp_pack is
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package t48_core_comp_pack is
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component t48_core
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component t48_core
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generic (
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generic (
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xtal_div_3_g : integer := 1;
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xtal_div_3_g : integer := 1;
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register_mnemonic_g : integer := 1;
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register_mnemonic_g : integer := 1;
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include_port1_g : integer := 1;
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include_port1_g : integer := 1;
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include_port2_g : integer := 1;
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include_port2_g : integer := 1;
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include_bus_g : integer := 1;
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include_bus_g : integer := 1;
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include_timer_g : integer := 1;
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include_timer_g : integer := 1;
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sample_t1_state_g : integer := 4
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sample_t1_state_g : integer := 4
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);
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);
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port (
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port (
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xtal_i : in std_logic;
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xtal_i : in std_logic;
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reset_i : in std_logic;
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reset_i : in std_logic;
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t0_i : in std_logic;
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t0_i : in std_logic;
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t0_o : out std_logic;
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t0_o : out std_logic;
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t0_dir_o : out std_logic;
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t0_dir_o : out std_logic;
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int_n_i : in std_logic;
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int_n_i : in std_logic;
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ea_i : in std_logic;
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ea_i : in std_logic;
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rd_n_o : out std_logic;
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rd_n_o : out std_logic;
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psen_n_o : out std_logic;
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psen_n_o : out std_logic;
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wr_n_o : out std_logic;
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wr_n_o : out std_logic;
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ale_o : out std_logic;
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ale_o : out std_logic;
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db_i : in std_logic_vector( 7 downto 0);
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db_i : in std_logic_vector( 7 downto 0);
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db_o : out std_logic_vector( 7 downto 0);
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db_o : out std_logic_vector( 7 downto 0);
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db_dir_o : out std_logic;
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db_dir_o : out std_logic;
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t1_i : in std_logic;
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t1_i : in std_logic;
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p2_i : in std_logic_vector( 7 downto 0);
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p2_i : in std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2_low_imp_o : out std_logic;
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p2_low_imp_o : out std_logic;
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p1_i : in std_logic_vector( 7 downto 0);
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p1_i : in std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_low_imp_o : out std_logic;
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p1_low_imp_o : out std_logic;
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prog_n_o : out std_logic;
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prog_n_o : out std_logic;
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clk_i : in std_logic;
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clk_i : in std_logic;
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en_clk_i : in std_logic;
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en_clk_i : in std_logic;
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xtal3_o : out std_logic;
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xtal3_o : out std_logic;
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dmem_addr_o : out std_logic_vector( 7 downto 0);
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dmem_addr_o : out std_logic_vector( 7 downto 0);
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dmem_we_o : out std_logic;
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dmem_we_o : out std_logic;
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dmem_data_i : in std_logic_vector( 7 downto 0);
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dmem_data_i : in std_logic_vector( 7 downto 0);
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dmem_data_o : out std_logic_vector( 7 downto 0);
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dmem_data_o : out std_logic_vector( 7 downto 0);
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pmem_addr_o : out std_logic_vector(11 downto 0);
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pmem_addr_o : out std_logic_vector(11 downto 0);
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pmem_data_i : in std_logic_vector( 7 downto 0)
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pmem_data_i : in std_logic_vector( 7 downto 0)
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);
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);
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end component;
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end component;
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component syn_rom
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component syn_rom
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generic (
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generic (
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address_width_g : positive := 10
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address_width_g : positive := 10
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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rom_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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rom_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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rom_data_o : out std_logic_vector(7 downto 0)
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rom_data_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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component syn_ram
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component syn_ram
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generic (
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generic (
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address_width_g : positive := 8
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address_width_g : positive := 8
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);
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);
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port (
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port (
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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ram_addr_i : in std_logic_vector(address_width_g-1 downto 0);
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ram_data_i : in std_logic_vector(7 downto 0);
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ram_data_i : in std_logic_vector(7 downto 0);
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ram_we_i : in std_logic;
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ram_we_i : in std_logic;
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ram_data_o : out std_logic_vector(7 downto 0)
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ram_data_o : out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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end t48_core_comp_pack;
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end t48_core_comp_pack;
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