#!/usr/bin/perl -w
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#!/usr/bin/perl -w
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#
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#
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# ############################################################################
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# ############################################################################
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#
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#
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# run_regression.pl
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# run_regression.pl
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#
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#
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# $Id: run_regression.pl,v 1.8 2004-09-12 00:30:53 arniml Exp $
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# $Id: run_regression.pl,v 1.8 2004-09-12 00:30:53 arniml Exp $
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#
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#
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# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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# Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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#
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#
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# All rights reserved
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# All rights reserved
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#
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#
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# ############################################################################
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# ############################################################################
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#
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#
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# Purpose:
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# Purpose:
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# ========
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# ========
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#
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#
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# Runs regression suite over all testcells found in $VERIF_DIR.
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# Runs regression suite over all testcells found in $VERIF_DIR.
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#
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#
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# run_regression.pl [-d]
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# run_regression.pl [-d]
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# -d : Perform a dump compare on each test with the i8039 simulator.
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# -d : Perform a dump compare on each test with the i8039 simulator.
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#
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#
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# The testcells are identified by searching for the .asm file(s).
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# The testcells are identified by searching for the .asm file(s).
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# Each testcell is built by calling the central Makefile.cell.
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# Each testcell is built by calling the central Makefile.cell.
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# The resulting hex-file is then copied to $SIM_DIR where the VHDL simulator
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# The resulting hex-file is then copied to $SIM_DIR where the VHDL simulator
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# is started.
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# is started.
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#
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#
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use strict;
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use strict;
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use Getopt::Std;
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use Getopt::Std;
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sub print_usage {
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sub print_usage {
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print <<EOU;
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print <<EOU;
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Runs regression tests in \$VERIF_DIR.
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Runs regression tests in \$VERIF_DIR.
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Usage:
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Usage:
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run_regression.pl [-d]
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run_regression.pl [-d]
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-d : Perform a dump compare on each test with the i8039 simulator.
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-d : Perform a dump compare on each test with the i8039 simulator.
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EOU
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EOU
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}
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}
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my %options;
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my %options;
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my (@asm_files, $asm_file);
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my (@asm_files, $asm_file);
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my (%cells, $cell, $cell_dir, $tag);
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my (%cells, $cell, $cell_dir, $tag);
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my $pwd;
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my $pwd;
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my $dump_compare = 0;
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my $dump_compare = 0;
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my $dump_compare_cell = 0;
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my $dump_compare_cell = 0;
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##############################################################################
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##############################################################################
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# Commands to call the different VHDL simulators.
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# Commands to call the different VHDL simulators.
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#
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#
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# GHDL
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# GHDL
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my $ghdl_simulator = './tb_behav_c0 --assert-level=error';
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my $ghdl_simulator = './tb_behav_c0 --assert-level=error';
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my $ghdl_simulator_vcd = $ghdl_simulator.' --vcd=temp.vcd';
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my $ghdl_simulator_vcd = $ghdl_simulator.' --vcd=temp.vcd';
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#
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#
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# Choose simulator:
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# Choose simulator:
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my $vhdl_simulator = $ghdl_simulator;
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my $vhdl_simulator = $ghdl_simulator;
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my $vhdl_simulator_vcd = $ghdl_simulator_vcd;
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my $vhdl_simulator_vcd = $ghdl_simulator_vcd;
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#
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#
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##############################################################################
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##############################################################################
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# process command line options
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# process command line options
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if (!getopts('d', \%options)) {
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if (!getopts('d', \%options)) {
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print_usage();
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print_usage();
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exit(1);
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exit(1);
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}
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}
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if (exists($options{'d'})) {
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if (exists($options{'d'})) {
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$dump_compare = 1;
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$dump_compare = 1;
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}
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}
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$pwd = `pwd`;
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$pwd = `pwd`;
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chomp($pwd);
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chomp($pwd);
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@asm_files = `find \$VERIF_DIR/black_box -name '*.asm'`;
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@asm_files = `find \$VERIF_DIR/black_box -name '*.asm'`;
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push(@asm_files, `find \$VERIF_DIR/white_box -name '*.asm'`);
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push(@asm_files, `find \$VERIF_DIR/white_box -name '*.asm'`);
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foreach $asm_file (@asm_files) {
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foreach $asm_file (@asm_files) {
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chomp($asm_file);
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chomp($asm_file);
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# strip off assembler file names
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# strip off assembler file names
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$asm_file =~ s/\/[^\/]+\.asm//;
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$asm_file =~ s/\/[^\/]+\.asm//;
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# strip off verification directory
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# strip off verification directory
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$asm_file =~ s/$ENV{'VERIF_DIR'}\///;
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$asm_file =~ s/$ENV{'VERIF_DIR'}\///;
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$cells{$asm_file} = 1;
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$cells{$asm_file} = 1;
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}
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}
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while (($cell, $tag) = each(%cells)) {
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while (($cell, $tag) = each(%cells)) {
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$cell_dir = "$ENV{'VERIF_DIR'}/$cell";
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$cell_dir = "$ENV{'VERIF_DIR'}/$cell";
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if (chdir($cell_dir)) {
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if (chdir($cell_dir)) {
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print("Processing $cell\n");
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print("Processing $cell\n");
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$dump_compare_cell = -e 'no_dump_compare' ? 0 : $dump_compare;
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$dump_compare_cell = -e 'no_dump_compare' ? 0 : $dump_compare;
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system('sh', '-c', 'rm -f $SIM_DIR/t48_rom.hex');
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system('sh', '-c', 'rm -f $SIM_DIR/t48_rom.hex');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell clean');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell clean');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell simu clean');
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system('sh', '-c', 'make -f $VERIF_DIR/include/Makefile.cell simu clean');
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if ($? == 0) {
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if ($? == 0) {
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chdir($ENV{'SIM_DIR'});
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chdir($ENV{'SIM_DIR'});
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system('sh', '-c', 'ls -l t48_rom.hex');
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system('sh', '-c', 'ls -l t48_rom.hex');
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system('sh', '-c', $dump_compare_cell > 0 ? $vhdl_simulator_vcd : $vhdl_simulator);
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system('sh', '-c', $dump_compare_cell > 0 ? $vhdl_simulator_vcd : $vhdl_simulator);
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if ($dump_compare_cell) {
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if ($dump_compare_cell) {
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system('sh', '-c', 'rm -f dump sim.dump vhdl.dump');
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system('sh', '-c', 'rm -f dump sim.dump vhdl.dump');
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system('sh', '-c',
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system('sh', '-c',
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'vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump');
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'vcd2vec.pl -s ../../sw/dump_compare.signals < temp.vcd | vec2dump.pl > vhdl.dump');
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system('sh', '-c', 'i8039 -f t48_rom.hex -x t48_ext_rom.hex -d > dump');
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system('sh', '-c', 'i8039 -f t48_rom.hex -x t48_ext_rom.hex -d > dump');
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system('sh', '-c', 'egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump');
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system('sh', '-c', 'egrep \':.+\|\' dump | sed -e \'s/[^|]*. *//\' > sim.dump');
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system('sh', '-c', 'diff -b -q sim.dump vhdl.dump');
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system('sh', '-c', 'diff -b -q sim.dump vhdl.dump');
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print("Dump Compare: ");
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print("Dump Compare: ");
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if ($? == 0) {
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if ($? == 0) {
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print("PASS\n");
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print("PASS\n");
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} else {
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} else {
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print("FAIL\n");
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print("FAIL\n");
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}
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}
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system('sh', '-c', 'rm -f dump sim.dump vhdl.dump temp.vcd');
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system('sh', '-c', 'rm -f dump sim.dump vhdl.dump temp.vcd');
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} elsif ($dump_compare) {
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} elsif ($dump_compare) {
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print("Dump Compare: Excluded\n");
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print("Dump Compare: Excluded\n");
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}
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}
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} else {
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} else {
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print("Error: Cannot make cell $cell!\n");
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print("Error: Cannot make cell $cell!\n");
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}
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}
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} else {
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} else {
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print("Error: Cannot change to directory $cell_dir!\n");
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print("Error: Cannot change to directory $cell_dir!\n");
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}
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}
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}
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}
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chdir($pwd);
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chdir($pwd);
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