-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Arithmetic Logic Unit (ALU).
|
-- The Arithmetic Logic Unit (ALU).
|
-- It contains the ALU core plus the Accumulator and the Temp Reg.
|
-- It contains the ALU core plus the Accumulator and the Temp Reg.
|
--
|
--
|
-- $Id: alu.vhd,v 1.4 2004-04-06 18:10:41 arniml Exp $
|
-- $Id: alu.vhd,v 1.5 2004-04-06 20:21:53 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
|
--
|
-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
|
--
|
--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
|
--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
use work.t48_pack.word_t;
|
use work.t48_pack.word_t;
|
use work.alu_pack.alu_op_t;
|
use work.alu_pack.alu_op_t;
|
|
|
entity alu is
|
entity alu is
|
|
|
port (
|
port (
|
-- Global Interface -------------------------------------------------------
|
-- Global Interface -------------------------------------------------------
|
clk_i : in std_logic;
|
clk_i : in std_logic;
|
res_i : in std_logic;
|
res_i : in std_logic;
|
en_clk_i : in boolean;
|
en_clk_i : in boolean;
|
-- T48 Bus Interface ------------------------------------------------------
|
-- T48 Bus Interface ------------------------------------------------------
|
data_i : in word_t;
|
data_i : in word_t;
|
data_o : out word_t;
|
data_o : out word_t;
|
write_accu_i : in boolean;
|
write_accu_i : in boolean;
|
write_shadow_i : in boolean;
|
write_shadow_i : in boolean;
|
write_temp_reg_i : in boolean;
|
write_temp_reg_i : in boolean;
|
read_alu_i : in boolean;
|
read_alu_i : in boolean;
|
-- Decoder Interface ------------------------------------------------------
|
-- Decoder Interface ------------------------------------------------------
|
carry_i : in std_logic;
|
carry_i : in std_logic;
|
carry_o : out std_logic;
|
carry_o : out std_logic;
|
aux_carry_i : in std_logic;
|
aux_carry_i : in std_logic;
|
aux_carry_o : out std_logic;
|
aux_carry_o : out std_logic;
|
alu_op_i : in alu_op_t;
|
alu_op_i : in alu_op_t;
|
use_carry_i : in boolean;
|
use_carry_i : in boolean;
|
da_low_i : in boolean;
|
da_low_i : in boolean;
|
da_high_i : in boolean;
|
da_high_i : in boolean;
|
da_overflow_o : out boolean;
|
da_overflow_o : out boolean;
|
accu_low_i : in boolean;
|
accu_low_i : in boolean;
|
p06_temp_reg_i : in boolean;
|
p06_temp_reg_i : in boolean;
|
p60_temp_reg_i : in boolean
|
p60_temp_reg_i : in boolean
|
);
|
);
|
|
|
end alu;
|
end alu;
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.clk_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.res_active_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.bus_idle_level_c;
|
use work.t48_pack.nibble_t;
|
use work.t48_pack.nibble_t;
|
use work.alu_pack.all;
|
use work.alu_pack.all;
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
use work.t48_tb_pack.tb_accu_s;
|
use work.t48_tb_pack.tb_accu_s;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
architecture rtl of alu is
|
architecture rtl of alu is
|
|
|
-- the Accumulator and Temp Reg
|
-- the Accumulator and Temp Reg
|
signal accumulator_q,
|
signal accumulator_q,
|
accu_shadow_q,
|
accu_shadow_q,
|
temp_req_q : word_t;
|
temp_req_q : word_t;
|
-- inputs to the ALU core
|
-- inputs to the ALU core
|
signal in_a_s,
|
signal in_a_s,
|
in_b_s : word_t;
|
in_b_s : word_t;
|
-- output of the ALU core
|
-- output of the ALU core
|
signal data_s : word_t;
|
signal data_s : word_t;
|
|
|
signal add_result_s : alu_operand_t;
|
signal add_result_s : alu_operand_t;
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process working_regs
|
-- Process working_regs
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implements the working registers:
|
-- Implements the working registers:
|
-- + Accumulator
|
-- + Accumulator
|
-- + Temp Reg
|
-- + Temp Reg
|
--
|
--
|
working_regs: process (res_i, clk_i)
|
working_regs: process (res_i, clk_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
accumulator_q <= (others => '0');
|
accumulator_q <= (others => '0');
|
accu_shadow_q <= (others => '0');
|
accu_shadow_q <= (others => '0');
|
temp_req_q <= (others => '0');
|
temp_req_q <= (others => '0');
|
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
|
if write_accu_i then
|
if write_accu_i then
|
if accu_low_i then
|
if accu_low_i then
|
accumulator_q(nibble_t'range) <= data_i(nibble_t'range);
|
accumulator_q(nibble_t'range) <= data_i(nibble_t'range);
|
else
|
else
|
accumulator_q <= data_i;
|
accumulator_q <= data_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if write_shadow_i then
|
if write_shadow_i then
|
-- write shadow directly from t48 data bus
|
-- write shadow directly from t48 data bus
|
accu_shadow_q <= data_i;
|
accu_shadow_q <= data_i;
|
else
|
else
|
-- default: update shadow Accumulator from real Accumulator
|
-- default: update shadow Accumulator from real Accumulator
|
accu_shadow_q <= accumulator_q;
|
accu_shadow_q <= accumulator_q;
|
end if;
|
end if;
|
|
|
if p06_temp_reg_i then
|
if p06_temp_reg_i then
|
-- low nibble of DA sequence
|
-- low nibble of DA sequence
|
temp_req_q <= "00000110";
|
temp_req_q <= "00000110";
|
elsif p60_temp_reg_i then
|
elsif p60_temp_reg_i then
|
-- high nibble of DA sequence
|
-- high nibble of DA sequence
|
temp_req_q <= "01100000";
|
temp_req_q <= "01100000";
|
elsif write_temp_reg_i then
|
elsif write_temp_reg_i then
|
-- normal load from T48 bus
|
-- normal load from T48 bus
|
temp_req_q <= data_i;
|
temp_req_q <= data_i;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process working_regs;
|
end process working_regs;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Build the inputs to the ALU core.
|
-- Build the inputs to the ALU core.
|
-- Input A:
|
-- Input A:
|
-- Unary operators use only Input A.
|
-- Unary operators use only Input A.
|
-- Is always fed from the shadow Accumulator.
|
-- Is always fed from the shadow Accumulator.
|
-- Assumption: It never happens that the Accumulator is written and then
|
-- Assumption: It never happens that the Accumulator is written and then
|
-- read for an ALU operation in the next cycle.
|
-- read for an ALU operation in the next cycle.
|
-- Its contents can thus be staged through the shadow Accu.
|
-- Its contents can thus be staged through the shadow Accu.
|
-- Input B:
|
-- Input B:
|
-- Is always fed from the Temp Reg.
|
-- Is always fed from the Temp Reg.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
in_a_s <= accu_shadow_q;
|
in_a_s <= accu_shadow_q;
|
in_b_s <= temp_req_q;
|
in_b_s <= temp_req_q;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process alu_core
|
-- Process alu_core
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implements the ALU core.
|
-- Implements the ALU core.
|
-- All operations defined in alu_op_t are handled here.
|
-- All operations defined in alu_op_t are handled here.
|
--
|
--
|
alu_core: process (in_a_s,
|
alu_core: process (in_a_s,
|
in_b_s,
|
in_b_s,
|
alu_op_i,
|
alu_op_i,
|
|
carry_i,
|
|
use_carry_i,
|
add_result_s)
|
add_result_s)
|
|
|
begin
|
begin
|
-- default assigments
|
-- default assigments
|
data_s <= (others => '0');
|
data_s <= (others => '0');
|
carry_o <= '0';
|
carry_o <= '0';
|
|
|
case alu_op_i is
|
case alu_op_i is
|
-- Operation: AND -------------------------------------------------------
|
-- Operation: AND -------------------------------------------------------
|
when ALU_AND =>
|
when ALU_AND =>
|
data_s <= in_a_s and in_b_s;
|
data_s <= in_a_s and in_b_s;
|
|
|
-- Operation: OR --------------------------------------------------------
|
-- Operation: OR --------------------------------------------------------
|
when ALU_OR =>
|
when ALU_OR =>
|
data_s <= in_a_s or in_b_s;
|
data_s <= in_a_s or in_b_s;
|
|
|
-- Operation: XOR -------------------------------------------------------
|
-- Operation: XOR -------------------------------------------------------
|
when ALU_XOR =>
|
when ALU_XOR =>
|
data_s <= in_a_s xor in_b_s;
|
data_s <= in_a_s xor in_b_s;
|
|
|
-- Operation: Add -------------------------------------------------------
|
-- Operation: Add -------------------------------------------------------
|
when ALU_ADD =>
|
when ALU_ADD =>
|
data_s <= add_result_s(data_s'range);
|
data_s <= add_result_s(data_s'range);
|
carry_o <= add_result_s(add_result_s'high);
|
carry_o <= add_result_s(add_result_s'high);
|
|
|
-- Operation: CPL -------------------------------------------------------
|
-- Operation: CPL -------------------------------------------------------
|
when ALU_CPL =>
|
when ALU_CPL =>
|
data_s <= not in_a_s;
|
data_s <= not in_a_s;
|
|
|
-- Operation: CLR -------------------------------------------------------
|
-- Operation: CLR -------------------------------------------------------
|
when ALU_CLR =>
|
when ALU_CLR =>
|
data_s <= (others => '0');
|
data_s <= (others => '0');
|
|
|
-- Operation: RL --------------------------------------------------------
|
-- Operation: RL --------------------------------------------------------
|
when ALU_RL =>
|
when ALU_RL =>
|
data_s(7 downto 1) <= in_a_s(6 downto 0);
|
data_s(7 downto 1) <= in_a_s(6 downto 0);
|
carry_o <= in_a_s(7);
|
carry_o <= in_a_s(7);
|
|
|
if use_carry_i then
|
if use_carry_i then
|
data_s(0) <= carry_i;
|
data_s(0) <= carry_i;
|
else
|
else
|
data_s(0) <= in_a_s(7);
|
data_s(0) <= in_a_s(7);
|
end if;
|
end if;
|
|
|
-- Operation: RR --------------------------------------------------------
|
-- Operation: RR --------------------------------------------------------
|
when ALU_RR =>
|
when ALU_RR =>
|
data_s(6 downto 0) <= in_a_s(7 downto 1);
|
data_s(6 downto 0) <= in_a_s(7 downto 1);
|
carry_o <= in_a_s(0);
|
carry_o <= in_a_s(0);
|
|
|
if use_carry_i then
|
if use_carry_i then
|
data_s(7) <= carry_i;
|
data_s(7) <= carry_i;
|
else
|
else
|
data_s(7) <= in_a_s(0);
|
data_s(7) <= in_a_s(0);
|
end if;
|
end if;
|
|
|
-- Operation: Swap ------------------------------------------------------
|
-- Operation: Swap ------------------------------------------------------
|
when ALU_SWAP =>
|
when ALU_SWAP =>
|
data_s(3 downto 0) <= in_a_s(7 downto 4);
|
data_s(3 downto 0) <= in_a_s(7 downto 4);
|
data_s(7 downto 4) <= in_a_s(3 downto 0);
|
data_s(7 downto 4) <= in_a_s(3 downto 0);
|
|
|
-- Operation: DEC -------------------------------------------------------
|
-- Operation: DEC -------------------------------------------------------
|
when ALU_DEC =>
|
when ALU_DEC =>
|
data_s <= add_result_s(data_s'range);
|
data_s <= add_result_s(data_s'range);
|
|
|
-- Operation: INC -------------------------------------------------------
|
-- Operation: INC -------------------------------------------------------
|
when ALU_INC =>
|
when ALU_INC =>
|
data_s <= add_result_s(data_s'range);
|
data_s <= add_result_s(data_s'range);
|
|
|
-- Operation CONCAT -----------------------------------------------------
|
-- Operation CONCAT -----------------------------------------------------
|
when ALU_CONCAT =>
|
when ALU_CONCAT =>
|
data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
|
data_s <= in_b_s(7 downto 4) & in_a_s(3 downto 0);
|
|
|
-- Operation: NOP -------------------------------------------------------
|
-- Operation: NOP -------------------------------------------------------
|
when ALU_NOP =>
|
when ALU_NOP =>
|
data_s <= in_a_s;
|
data_s <= in_a_s;
|
|
|
when others =>
|
when others =>
|
-- pragma translate_off
|
-- pragma translate_off
|
assert false
|
assert false
|
report "Unknown ALU operation selected!"
|
report "Unknown ALU operation selected!"
|
severity error;
|
severity error;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
end case;
|
end case;
|
|
|
end process alu_core;
|
end process alu_core;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process adder
|
-- Process adder
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implements the adder used by several instructions.
|
-- Implements the adder used by several instructions.
|
-- This way of modelling the adder forces resource sharing of:
|
-- This way of modelling the adder forces resource sharing of:
|
-- * ADD
|
-- * ADD
|
-- * INC
|
-- * INC
|
-- * DEC
|
-- * DEC
|
--
|
--
|
adder: process (in_a_s,
|
adder: process (in_a_s,
|
in_b_s,
|
in_b_s,
|
alu_op_i,
|
alu_op_i,
|
carry_i,
|
carry_i,
|
use_carry_i)
|
use_carry_i)
|
|
|
variable add_a_v, add_b_v : alu_operand_t;
|
variable add_a_v, add_b_v : alu_operand_t;
|
variable result_v : alu_operand_t;
|
variable result_v : alu_operand_t;
|
variable c_v : std_logic;
|
variable c_v : std_logic;
|
variable aux_c_v : std_logic_vector(1 downto 0);
|
variable aux_c_v : std_logic_vector(1 downto 0);
|
|
|
begin
|
begin
|
-- Carry Selection --------------------------------------------------------
|
-- Carry Selection --------------------------------------------------------
|
if use_carry_i then
|
if use_carry_i then
|
c_v := carry_i;
|
c_v := carry_i;
|
else
|
else
|
c_v := '0';
|
c_v := '0';
|
end if;
|
end if;
|
|
|
-- Operand Selection ------------------------------------------------------
|
-- Operand Selection ------------------------------------------------------
|
-- defaults for ADD
|
-- defaults for ADD
|
add_a_v := '0' & in_a_s;
|
add_a_v := '0' & in_a_s;
|
add_b_v := '0' & in_b_s;
|
add_b_v := '0' & in_b_s;
|
|
|
case alu_op_i is
|
case alu_op_i is
|
when ALU_INC =>
|
when ALU_INC =>
|
add_b_v := "000000001";
|
add_b_v := "000000001";
|
when ALU_DEC =>
|
when ALU_DEC =>
|
add_b_v := "111111111";
|
add_b_v := "111111111";
|
when others =>
|
when others =>
|
null;
|
null;
|
end case;
|
end case;
|
|
|
-- The Adder --------------------------------------------------------------
|
-- The Adder --------------------------------------------------------------
|
result_v := UNSIGNED(add_a_v) +
|
result_v := UNSIGNED(add_a_v) +
|
UNSIGNED(add_b_v) +
|
UNSIGNED(add_b_v) +
|
CONV_UNSIGNED(c_v, alu_operand_t'length);
|
CONV_UNSIGNED(c_v, alu_operand_t'length);
|
|
|
add_result_s <= result_v;
|
add_result_s <= result_v;
|
|
|
-- Auxiliary Carry --------------------------------------------------------
|
-- Auxiliary Carry --------------------------------------------------------
|
aux_c_v := in_a_s(4) & in_b_s(4);
|
aux_c_v := in_a_s(4) & in_b_s(4);
|
|
|
case aux_c_v is
|
case aux_c_v is
|
when "00" | "11" =>
|
when "00" | "11" =>
|
if result_v(4) = '1' then
|
if result_v(4) = '1' then
|
aux_carry_o <= '1';
|
aux_carry_o <= '1';
|
end if;
|
end if;
|
|
|
when "01" | "10" =>
|
when "01" | "10" =>
|
if result_v(4) = '0' then
|
if result_v(4) = '0' then
|
aux_carry_o <= '1';
|
aux_carry_o <= '1';
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
aux_carry_o <= '0';
|
aux_carry_o <= '0';
|
null;
|
null;
|
|
|
end case;
|
end case;
|
|
|
end process adder;
|
end process adder;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process da_overflow
|
-- Process da_overflow
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Detect overflow situation during DA sequence.
|
-- Detect overflow situation during DA sequence.
|
--
|
--
|
da_overflow: process (accu_shadow_q,
|
da_overflow: process (accu_shadow_q,
|
da_high_i)
|
da_high_i)
|
|
|
variable da_nibble_v : nibble_t;
|
variable da_nibble_v : nibble_t;
|
|
|
function da_overflow_f(data : in nibble_t) return boolean is
|
function da_overflow_f(data : in nibble_t) return boolean is
|
variable overflow_v : boolean;
|
variable overflow_v : boolean;
|
begin
|
begin
|
case data is
|
case data is
|
when "1010" |
|
when "1010" |
|
"1011" |
|
"1011" |
|
"1100" |
|
"1100" |
|
"1101" |
|
"1101" |
|
"1110" |
|
"1110" |
|
"1111" =>
|
"1111" =>
|
overflow_v := true;
|
overflow_v := true;
|
when others =>
|
when others =>
|
overflow_v := false;
|
overflow_v := false;
|
end case;
|
end case;
|
|
|
return(overflow_v);
|
return(overflow_v);
|
end;
|
end;
|
|
|
begin
|
begin
|
if da_high_i then
|
if da_high_i then
|
da_nibble_v := accu_shadow_q(7 downto 4);
|
da_nibble_v := accu_shadow_q(7 downto 4);
|
else
|
else
|
da_nibble_v := accu_shadow_q(3 downto 0);
|
da_nibble_v := accu_shadow_q(3 downto 0);
|
end if;
|
end if;
|
|
|
da_overflow_o <= da_overflow_f(da_nibble_v);
|
da_overflow_o <= da_overflow_f(da_nibble_v);
|
|
|
end process da_overflow;
|
end process da_overflow;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Testbench support.
|
-- Testbench support.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
tb_accu_s <= accumulator_q;
|
tb_accu_s <= accumulator_q;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output Multiplexer.
|
-- Output Multiplexer.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
data_o <= data_s
|
data_o <= data_s
|
when read_alu_i else
|
when read_alu_i else
|
(others => bus_idle_level_c);
|
(others => bus_idle_level_c);
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.4 2004/04/06 18:10:41 arniml
|
|
-- rework adder and force resource sharing between ADD, INC and DEC
|
|
--
|
-- Revision 1.3 2004/04/04 14:18:52 arniml
|
-- Revision 1.3 2004/04/04 14:18:52 arniml
|
-- add measures to implement XCHD
|
-- add measures to implement XCHD
|
--
|
--
|
-- Revision 1.2 2004/03/28 21:08:51 arniml
|
-- Revision 1.2 2004/03/28 21:08:51 arniml
|
-- support for DA instruction
|
-- support for DA instruction
|
--
|
--
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
