-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Clock Control unit.
|
-- The Clock Control unit.
|
-- Clock States and Machine Cycles are generated here.
|
-- Clock States and Machine Cycles are generated here.
|
--
|
--
|
-- $Id: clock_ctrl.vhd,v 1.2 2004-03-28 12:55:06 arniml Exp $
|
-- $Id: clock_ctrl.vhd,v 1.3 2004-04-18 18:56:23 arniml Exp $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
|
--
|
-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
|
--
|
--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
|
--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
use work.t48_pack.all;
|
use work.t48_pack.all;
|
|
|
entity clock_ctrl is
|
entity clock_ctrl is
|
|
|
generic (
|
generic (
|
-- divide XTAL1 by 3 to derive Clock States
|
-- divide XTAL1 by 3 to derive Clock States
|
xtal_div_3_g : integer := 1
|
xtal_div_3_g : integer := 1
|
);
|
);
|
|
|
port (
|
port (
|
clk_i : in std_logic;
|
clk_i : in std_logic;
|
xtal_i : in std_logic;
|
xtal_i : in std_logic;
|
res_i : in std_logic;
|
res_i : in std_logic;
|
en_clk_i : in boolean;
|
en_clk_i : in boolean;
|
xtal3_o : out boolean;
|
xtal3_o : out boolean;
|
multi_cycle_i : in boolean;
|
multi_cycle_i : in boolean;
|
assert_psen_i : in boolean;
|
assert_psen_i : in boolean;
|
assert_prog_i : in boolean;
|
assert_prog_i : in boolean;
|
assert_rd_i : in boolean;
|
assert_rd_i : in boolean;
|
assert_wr_i : in boolean;
|
assert_wr_i : in boolean;
|
mstate_o : out mstate_t;
|
mstate_o : out mstate_t;
|
second_cycle_o : out boolean;
|
second_cycle_o : out boolean;
|
ale_o : out boolean;
|
ale_o : out boolean;
|
psen_o : out boolean;
|
psen_o : out boolean;
|
prog_o : out boolean;
|
prog_o : out boolean;
|
rd_o : out boolean;
|
rd_o : out boolean;
|
wr_o : out boolean
|
wr_o : out boolean
|
);
|
);
|
|
|
end clock_ctrl;
|
end clock_ctrl;
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
architecture rtl of clock_ctrl is
|
architecture rtl of clock_ctrl is
|
|
|
-- The three XTAL1 cycles.
|
-- The three XTAL1 cycles.
|
signal xtal_q : unsigned(1 downto 0);
|
signal xtal_q : unsigned(1 downto 0);
|
signal xtal1_s,
|
signal xtal1_s,
|
xtal2_s,
|
xtal2_s,
|
xtal3_s : boolean;
|
xtal3_s : boolean;
|
signal x1_s,
|
signal x1_s,
|
x2_s,
|
x2_s,
|
x3_s : std_logic;
|
x3_s : std_logic;
|
|
|
|
|
-- The five clock states.
|
-- The five clock states.
|
signal mstate_q : mstate_t;
|
signal mstate_q : mstate_t;
|
|
|
signal ale_q : boolean;
|
signal ale_q : boolean;
|
signal psen_q : boolean;
|
signal psen_q : boolean;
|
signal prog_q : boolean;
|
signal prog_q : boolean;
|
signal rd_q : boolean;
|
signal rd_q : boolean;
|
signal wr_q : boolean;
|
signal wr_q : boolean;
|
|
|
|
|
-- The Machine Cycle marker.
|
-- The Machine Cycle marker.
|
signal second_cycle_q : boolean;
|
signal second_cycle_q : boolean;
|
signal multi_cycle_q : boolean;
|
signal multi_cycle_q : boolean;
|
|
|
begin
|
begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Verify the generics
|
-- Verify the generics
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
|
|
-- XTAL1 divide by 3 --------------------------------------------------------
|
-- XTAL1 divide by 3 --------------------------------------------------------
|
assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0)
|
assert (xtal_div_3_g = 1) or (xtal_div_3_g = 0)
|
report "xtal_div_3_g must be either 1 or 0!"
|
report "xtal_div_3_g must be either 1 or 0!"
|
severity failure;
|
severity failure;
|
|
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Divide XTAL1 by 3 to derive Clock States.
|
-- Divide XTAL1 by 3 to derive Clock States.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
use_xtal_div: if xtal_div_3_g = 1 generate
|
use_xtal_div: if xtal_div_3_g = 1 generate
|
xtal: process (res_i, xtal_i)
|
xtal: process (res_i, xtal_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
|
|
elsif xtal_i'event and xtal_i = clk_active_c then
|
elsif xtal_i'event and xtal_i = clk_active_c then
|
if xtal_q < 2 then
|
if xtal_q < 2 then
|
xtal_q <= xtal_q + 1;
|
xtal_q <= xtal_q + 1;
|
else
|
else
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process xtal;
|
end process xtal;
|
|
|
x1_s <= '1'
|
x1_s <= '1'
|
when xtal_q = 0 else
|
when xtal_q = 0 else
|
'0';
|
'0';
|
x2_s <= '1'
|
x2_s <= '1'
|
when xtal_q = 1 else
|
when xtal_q = 1 else
|
'0';
|
'0';
|
x3_s <= '1'
|
x3_s <= '1'
|
when xtal_q = 2 else
|
when xtal_q = 2 else
|
'0';
|
'0';
|
|
|
end generate;
|
end generate;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- XTAL1 is used directly for Clock States.
|
-- XTAL1 is used directly for Clock States.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
no_xtal_div: if xtal_div_3_g = 0 generate
|
no_xtal_div: if xtal_div_3_g = 0 generate
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
xtal_q <= CONV_UNSIGNED(0, 2);
|
|
|
x1_s <= '1';
|
x1_s <= '1';
|
x2_s <= '1';
|
x2_s <= '1';
|
x3_s <= '1';
|
x3_s <= '1';
|
|
|
end generate;
|
end generate;
|
|
|
-- And finally the boolean flags --------------------------------------------
|
-- And finally the boolean flags --------------------------------------------
|
xtal1_s <= to_boolean(x1_s);
|
xtal1_s <= to_boolean(x1_s);
|
xtal2_s <= to_boolean(x2_s);
|
xtal2_s <= to_boolean(x2_s);
|
xtal3_s <= to_boolean(x3_s);
|
xtal3_s <= to_boolean(x3_s);
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process external_signal
|
-- Process external_signal
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Control signals ALE, PSEN, PROG and RD/WR are generated here.
|
-- Control signals ALE, PSEN, PROG and RD/WR are generated here.
|
--
|
--
|
external_signals: process (res_i, xtal_i)
|
external_signals: process (res_i, xtal_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
ale_q <= false;
|
ale_q <= false;
|
psen_q <= false;
|
psen_q <= false;
|
prog_q <= false;
|
prog_q <= false;
|
rd_q <= false;
|
rd_q <= false;
|
wr_q <= false;
|
wr_q <= false;
|
|
|
elsif xtal_i'event and xtal_i = clk_active_c then
|
elsif xtal_i'event and xtal_i = clk_active_c then
|
|
|
case mstate_q is
|
case mstate_q is
|
when MSTATE5 =>
|
when MSTATE5 =>
|
-- RD, WR are set at the end of XTAL2 of first machine cycle
|
-- RD, WR are set at the end of XTAL2 of first machine cycle
|
if xtal2_s and not second_cycle_q then
|
if xtal2_s and not second_cycle_q then
|
if assert_rd_i then
|
if assert_rd_i then
|
rd_q <= true;
|
rd_q <= true;
|
end if;
|
end if;
|
if assert_wr_i then
|
if assert_wr_i then
|
wr_q <= true;
|
wr_q <= true;
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
when MSTATE1 =>
|
when MSTATE1 =>
|
if xtal3_s then
|
if xtal3_s then
|
psen_q <= false;
|
psen_q <= false;
|
end if;
|
end if;
|
|
|
when MSTATE2 =>
|
when MSTATE2 =>
|
if xtal2_s then
|
if xtal2_s then
|
-- RD, WR are removed at the end of XTAL3 of second machine cycle
|
-- RD, WR are removed at the end of XTAL3 of second machine cycle
|
rd_q <= false;
|
rd_q <= false;
|
wr_q <= false;
|
wr_q <= false;
|
-- PROG is removed at the and of XTAL3 of second machine cycle
|
-- PROG is removed at the and of XTAL3 of second machine cycle
|
prog_q <= false;
|
prog_q <= false;
|
end if;
|
end if;
|
|
|
when MSTATE3 =>
|
when MSTATE3 =>
|
-- ALE is set at the end of XTAL2 of every machine cycle
|
-- ALE is set at the end of XTAL2 of every machine cycle
|
if xtal2_s then
|
if xtal2_s then
|
ale_q <= true;
|
ale_q <= true;
|
end if;
|
end if;
|
|
|
when MSTATE4 =>
|
when MSTATE4 =>
|
if xtal3_s then
|
if xtal3_s then
|
-- PSEN is set at the end of XTAL3
|
-- PSEN is set at the end of XTAL3
|
if assert_psen_i then
|
if assert_psen_i then
|
psen_q <= true;
|
psen_q <= true;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
-- PROG is set at the and of XTAL2
|
-- PROG is set at the and of XTAL2
|
if xtal2_s and multi_cycle_q and not second_cycle_q and
|
if xtal2_s and multi_cycle_q and not second_cycle_q and
|
assert_prog_i then
|
assert_prog_i then
|
prog_q <= true;
|
prog_q <= true;
|
end if;
|
end if;
|
|
|
-- ALE is removed at the end of XTAL2 of every machine cycle
|
-- ALE is removed at the end of XTAL2 of every machine cycle
|
if xtal2_s then
|
if xtal2_s then
|
ale_q <= false;
|
ale_q <= false;
|
end if;
|
end if;
|
|
|
when others =>
|
when others =>
|
-- recover when states are out of sync
|
-- recover when states are out of sync
|
ale_q <= false;
|
ale_q <= false;
|
psen_q <= false;
|
psen_q <= false;
|
prog_q <= false;
|
prog_q <= false;
|
rd_q <= false;
|
rd_q <= false;
|
wr_q <= false;
|
wr_q <= false;
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
|
end process external_signals;
|
end process external_signals;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process states
|
-- Process states
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- The Clock State controller.
|
-- The Clock State controller.
|
--
|
--
|
states: process (res_i, clk_i)
|
states: process (res_i, clk_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
mstate_q <= MSTATE1;
|
-- Reset machine state to MSTATE3
|
|
-- This allows a proper instruction fetch for the first real instruction
|
|
-- after reset.
|
|
-- The MSTATE3 is part of a virtual NOP that has no MSTATE1 and MSTATE2.
|
|
mstate_q <= MSTATE3;
|
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
|
case mstate_q is
|
case mstate_q is
|
when MSTATE5 =>
|
when MSTATE5 =>
|
mstate_q <= MSTATE1;
|
mstate_q <= MSTATE1;
|
|
|
when MSTATE1 =>
|
when MSTATE1 =>
|
mstate_q <= MSTATE2;
|
mstate_q <= MSTATE2;
|
|
|
when MSTATE2 =>
|
when MSTATE2 =>
|
mstate_q <= MSTATE3;
|
mstate_q <= MSTATE3;
|
|
|
when MSTATE3 =>
|
when MSTATE3 =>
|
mstate_q <= MSTATE4;
|
mstate_q <= MSTATE4;
|
|
|
when MSTATE4 =>
|
when MSTATE4 =>
|
mstate_q <= MSTATE5;
|
mstate_q <= MSTATE5;
|
|
|
when others =>
|
when others =>
|
-- recover when states are out of sync
|
-- recover when states are out of sync
|
mstate_q <= MSTATE1;
|
mstate_q <= MSTATE1;
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
assert false
|
assert false
|
report "Encoding of Clock States failed!"
|
report "Encoding of Clock States failed!"
|
severity error;
|
severity error;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
end case;
|
end case;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process states;
|
end process states;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process machine_cycle
|
-- Process machine_cycle
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Keep track of machine cycles.
|
-- Keep track of machine cycles.
|
-- Basically, this means to differ between first and second cycle.
|
-- Basically, this means to differ between first and second cycle.
|
--
|
--
|
machine_cycle: process (res_i, clk_i)
|
machine_cycle: process (res_i, clk_i)
|
variable state2_v, state5_v : boolean;
|
variable state2_v, state5_v : boolean;
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
multi_cycle_q <= false;
|
multi_cycle_q <= false;
|
second_cycle_q <= false;
|
second_cycle_q <= false;
|
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
|
state2_v := mstate_q = MSTATE2;
|
state2_v := mstate_q = MSTATE2;
|
state5_v := mstate_q = MSTATE5;
|
state5_v := mstate_q = MSTATE5;
|
|
|
-- multi cycle information is delivered in State 2 from the decoder
|
-- multi cycle information is delivered in State 2 from the decoder
|
if state2_v and multi_cycle_i then
|
if state2_v and multi_cycle_i then
|
multi_cycle_q <= true;
|
multi_cycle_q <= true;
|
end if;
|
end if;
|
|
|
-- mark second machine cycle
|
-- mark second machine cycle
|
if multi_cycle_q and state5_v then
|
if multi_cycle_q and state5_v then
|
second_cycle_q <= true;
|
second_cycle_q <= true;
|
end if;
|
end if;
|
|
|
-- reset at end of second machine cycle
|
-- reset at end of second machine cycle
|
if state5_v and
|
if state5_v and
|
(not multi_cycle_q or
|
(multi_cycle_q and second_cycle_q) then
|
(multi_cycle_q and second_cycle_q)) then
|
|
multi_cycle_q <= false;
|
multi_cycle_q <= false;
|
second_cycle_q <= false;
|
second_cycle_q <= false;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process machine_cycle;
|
end process machine_cycle;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output assignments
|
-- Output assignments
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
xtal3_o <= xtal3_s;
|
xtal3_o <= xtal3_s;
|
mstate_o <= mstate_q;
|
mstate_o <= mstate_q;
|
second_cycle_o <= second_cycle_q;
|
second_cycle_o <= second_cycle_q;
|
ale_o <= ale_q;
|
ale_o <= ale_q;
|
psen_o <= psen_q;
|
psen_o <= psen_q;
|
prog_o <= prog_q;
|
prog_o <= prog_q;
|
rd_o <= rd_q;
|
rd_o <= rd_q;
|
wr_o <= wr_q;
|
wr_o <= wr_q;
|
|
|
end rtl;
|
end rtl;
|
|
|
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File History:
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-- File History:
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--
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--
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-- $Log: not supported by cvs2svn $
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-- $Log: not supported by cvs2svn $
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-- Revision 1.2 2004/03/28 12:55:06 arniml
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-- move code for PROG out of if-branch for xtal3_s
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--
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- Revision 1.1 2004/03/23 21:31:52 arniml
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-- initial check-in
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-- initial check-in
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--
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--
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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