-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The Data Memory control unit.
|
-- The Data Memory control unit.
|
-- All accesses to the Data Memory are managed here.
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-- All accesses to the Data Memory are managed here.
|
--
|
--
|
-- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $
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-- $Id: dmem_ctrl.vhd,v 1.5 2006-06-20 01:07:16 arniml Exp $
|
--
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--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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--
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-- All rights reserved
|
-- All rights reserved
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--
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--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
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--
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
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--
|
--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
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--
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--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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use work.t48_pack.dmem_addr_t;
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use work.t48_pack.dmem_addr_t;
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use work.t48_pack.word_t;
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use work.t48_pack.word_t;
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use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
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use work.t48_dmem_ctrl_pack.dmem_addr_ident_t;
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|
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entity t48_dmem_ctrl is
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entity t48_dmem_ctrl is
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|
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port (
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port (
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-- Global Interface -------------------------------------------------------
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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en_clk_i : in boolean;
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-- Control Interface ------------------------------------------------------
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-- Control Interface ------------------------------------------------------
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data_i : in word_t;
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data_i : in word_t;
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write_dmem_addr_i : in boolean;
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write_dmem_addr_i : in boolean;
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write_dmem_i : in boolean;
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write_dmem_i : in boolean;
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read_dmem_i : in boolean;
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read_dmem_i : in boolean;
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addr_type_i : in dmem_addr_ident_t;
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addr_type_i : in dmem_addr_ident_t;
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bank_select_i : in std_logic;
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bank_select_i : in std_logic;
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data_o : out word_t;
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data_o : out word_t;
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-- Data Memory Interface --------------------------------------------------
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-- Data Memory Interface --------------------------------------------------
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dmem_data_i : in word_t;
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dmem_data_i : in word_t;
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dmem_addr_o : out dmem_addr_t;
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dmem_addr_o : out dmem_addr_t;
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dmem_we_o : out std_logic;
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dmem_we_o : out std_logic;
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dmem_data_o : out word_t
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dmem_data_o : out word_t
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);
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);
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|
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end t48_dmem_ctrl;
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end t48_dmem_ctrl;
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|
|
|
|
library ieee;
|
library ieee;
|
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
|
|
use work.t48_pack.clk_active_c;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.to_stdLogic;
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use work.t48_pack.to_stdLogic;
|
|
|
use work.t48_dmem_ctrl_pack.all;
|
use work.t48_dmem_ctrl_pack.all;
|
|
|
architecture rtl of t48_dmem_ctrl is
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architecture rtl of t48_dmem_ctrl is
|
|
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signal dmem_addr_s,
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signal dmem_addr_s,
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dmem_addr_q : dmem_addr_t;
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dmem_addr_q : dmem_addr_t;
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begin
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begin
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
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-- Process addr_decode
|
-- Process addr_decode
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--
|
--
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-- Purpose:
|
-- Purpose:
|
-- Decode/multiplex the address information for the Data Memory.
|
-- Decode/multiplex the address information for the Data Memory.
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--
|
--
|
addr_decode: process (data_i,
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addr_decode: process (data_i,
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addr_type_i,
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addr_type_i,
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bank_select_i,
|
bank_select_i,
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dmem_addr_q)
|
dmem_addr_q)
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variable stack_addr_v : unsigned(5 downto 0);
|
variable stack_addr_v : unsigned(5 downto 0);
|
begin
|
begin
|
-- default assignment
|
-- default assignment
|
dmem_addr_s <= dmem_addr_q;
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dmem_addr_s <= dmem_addr_q;
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stack_addr_v := (others => '0');
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stack_addr_v := (others => '0');
|
|
|
case addr_type_i is
|
case addr_type_i is
|
when DM_PLAIN =>
|
when DM_PLAIN =>
|
dmem_addr_s <= data_i;
|
dmem_addr_s <= data_i;
|
|
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when DM_REG =>
|
when DM_REG =>
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dmem_addr_s <= (others => '0');
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dmem_addr_s <= (others => '0');
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dmem_addr_s(2 downto 0) <= data_i(2 downto 0);
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dmem_addr_s(2 downto 0) <= data_i(2 downto 0);
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-- implement bank switching
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-- implement bank switching
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if bank_select_i = '1' then
|
if bank_select_i = '1' then
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-- dmem address 24 - 31: access proper set
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-- dmem address 24 - 31: access proper set
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dmem_addr_s(4 downto 3) <= "11";
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dmem_addr_s(4 downto 3) <= "11";
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end if;
|
end if;
|
|
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when DM_STACK =>
|
when DM_STACK =>
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-- build address from stack pointer
|
-- build address from stack pointer
|
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
|
stack_addr_v(3 downto 1) := unsigned(data_i(2 downto 0));
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-- dmem address 8 - 23
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-- dmem address 8 - 23
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stack_addr_v := stack_addr_v + 8;
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stack_addr_v := stack_addr_v + 8;
|
|
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dmem_addr_s <= (others => '0');
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dmem_addr_s <= (others => '0');
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dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
|
dmem_addr_s(5 downto 0) <= std_logic_vector(stack_addr_v);
|
|
|
when DM_STACK_HIGH =>
|
when DM_STACK_HIGH =>
|
dmem_addr_s(0) <= '1';
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dmem_addr_s(0) <= '1';
|
|
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when others =>
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when others =>
|
-- do nothing
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-- do nothing
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
assert false
|
assert false
|
report "Unknown address type identification for Data Memory controller!"
|
report "Unknown address type identification for Data Memory controller!"
|
severity error;
|
severity error;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
end case;
|
end case;
|
|
|
end process addr_decode;
|
end process addr_decode;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process dmem_addr_reg
|
-- Process dmem_addr_reg
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--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Implements the Data Memory Address Register.
|
-- Implements the Data Memory Address Register.
|
-- This register is required to hold the address during a write operation
|
-- This register is required to hold the address during a write operation
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-- as we cannot hold the address in the input register of the
|
-- as we cannot hold the address in the input register of the
|
-- synchronous RAM (no clock suppression/gating).
|
-- synchronous RAM (no clock suppression/gating).
|
--
|
--
|
-- NOTE: May be obsoleted by clock enable feature of generic RTL RAM.
|
-- NOTE: May be obsoleted by clock enable feature of generic RTL RAM.
|
--
|
--
|
dmem_addr_reg: process (res_i, clk_i)
|
dmem_addr_reg: process (res_i, clk_i)
|
begin
|
begin
|
if res_i = res_active_c then
|
if res_i = res_active_c then
|
dmem_addr_q <= (others => '0');
|
dmem_addr_q <= (others => '0');
|
|
|
elsif clk_i'event and clk_i = clk_active_c then
|
elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
|
if write_dmem_addr_i then
|
if write_dmem_addr_i then
|
dmem_addr_q <= dmem_addr_s;
|
dmem_addr_q <= dmem_addr_s;
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process dmem_addr_reg;
|
end process dmem_addr_reg;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output mapping.
|
-- Output mapping.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
dmem_addr_o <= dmem_addr_s
|
dmem_addr_o <= dmem_addr_s
|
when write_dmem_addr_i and en_clk_i else
|
when write_dmem_addr_i and en_clk_i else
|
dmem_addr_q;
|
dmem_addr_q;
|
|
|
-- data from bus is fed through
|
-- data from bus is fed through
|
dmem_data_o <= data_i;
|
dmem_data_o <= data_i;
|
|
|
-- data to bus is enabled upon read request
|
-- data to bus is enabled upon read request
|
data_o <= dmem_data_i
|
data_o <= dmem_data_i
|
when read_dmem_i else
|
when read_dmem_i else
|
(others => bus_idle_level_c);
|
(others => bus_idle_level_c);
|
|
|
-- write enable to Data Memory is fed through
|
-- write enable to Data Memory is fed through
|
dmem_we_o <= to_stdLogic(write_dmem_i);
|
dmem_we_o <= to_stdLogic(write_dmem_i);
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
-- Revision 1.4 2005/06/11 10:08:43 arniml
|
-- Revision 1.4 2005/06/11 10:08:43 arniml
|
-- introduce prefix 't48_' for all packages, entities and configurations
|
-- introduce prefix 't48_' for all packages, entities and configurations
|
--
|
--
|
-- Revision 1.3 2004/04/24 23:44:25 arniml
|
-- Revision 1.3 2004/04/24 23:44:25 arniml
|
-- move from std_logic_arith to numeric_std
|
-- move from std_logic_arith to numeric_std
|
--
|
--
|
-- Revision 1.2 2004/04/18 18:58:29 arniml
|
-- Revision 1.2 2004/04/18 18:58:29 arniml
|
-- clean up sensitivity list
|
-- clean up sensitivity list
|
--
|
--
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- Revision 1.1 2004/03/23 21:31:52 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
