-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
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-- The Program Status Word (PSW).
|
-- The Program Status Word (PSW).
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-- Implements the PSW with its special bits.
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-- Implements the PSW with its special bits.
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--
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--
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-- $Id: psw.vhd,v 1.4 2004-04-18 18:59:01 arniml Exp $
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-- $Id: psw.vhd,v 1.5 2004-04-24 11:25:39 arniml Exp $
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--
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--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
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--
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-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
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--
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--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
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--
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--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
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--
|
-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
--
|
--
|
-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
|
|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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use work.t48_pack.word_t;
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use work.t48_pack.word_t;
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|
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entity psw is
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entity psw is
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|
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port (
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port (
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-- Global Interface -------------------------------------------------------
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-- Global Interface -------------------------------------------------------
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clk_i : in std_logic;
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clk_i : in std_logic;
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res_i : in std_logic;
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res_i : in std_logic;
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en_clk_i : in boolean;
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en_clk_i : in boolean;
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-- T48 Bus Interface ------------------------------------------------------
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-- T48 Bus Interface ------------------------------------------------------
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data_i : in word_t;
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data_i : in word_t;
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data_o : out word_t;
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data_o : out word_t;
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read_psw_i : in boolean;
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read_psw_i : in boolean;
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read_sp_i : in boolean;
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read_sp_i : in boolean;
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write_psw_i : in boolean;
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write_psw_i : in boolean;
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write_sp_i : in boolean;
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write_sp_i : in boolean;
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-- Decoder Interface ------------------------------------------------------
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-- Decoder Interface ------------------------------------------------------
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special_data_i : in std_logic;
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special_data_i : in std_logic;
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inc_stackp_i : in boolean;
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inc_stackp_i : in boolean;
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dec_stackp_i : in boolean;
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dec_stackp_i : in boolean;
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write_carry_i : in boolean;
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write_carry_i : in boolean;
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write_aux_carry_i : in boolean;
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write_aux_carry_i : in boolean;
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write_f0_i : in boolean;
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write_f0_i : in boolean;
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write_bs_i : in boolean;
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write_bs_i : in boolean;
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carry_o : out std_logic;
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carry_o : out std_logic;
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aux_carry_i : in std_logic;
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aux_carry_i : in std_logic;
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aux_carry_o : out std_logic;
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aux_carry_o : out std_logic;
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f0_o : out std_logic;
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f0_o : out std_logic;
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bs_o : out std_logic
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bs_o : out std_logic
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);
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);
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|
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end psw;
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end psw;
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|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
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use work.t48_pack.clk_active_c;
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use work.t48_pack.clk_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.res_active_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.bus_idle_level_c;
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use work.t48_pack.nibble_t;
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use work.t48_pack.nibble_t;
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|
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architecture rtl of psw is
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architecture rtl of psw is
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|
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-- special bit positions in PSW
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-- special bit positions in PSW
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constant carry_c : natural := 3;
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constant carry_c : natural := 3;
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constant aux_carry_c : natural := 2;
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constant aux_carry_c : natural := 2;
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constant f0_c : natural := 1;
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constant f0_c : natural := 1;
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constant bs_c : natural := 0;
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constant bs_c : natural := 0;
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|
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-- the PSW register
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-- the PSW register
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signal psw_q : nibble_t;
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signal psw_q : nibble_t;
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-- the Stack Pointer
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-- the Stack Pointer
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signal sp_q : unsigned(2 downto 0);
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signal sp_q : unsigned(2 downto 0);
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|
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-- pragma translate_off
|
-- pragma translate_off
|
signal psw_s : word_t;
|
signal psw_s : word_t;
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signal dummy_s : std_logic;
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-- pragma translate_on
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-- pragma translate_on
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|
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begin
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begin
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|
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- Process psw_reg
|
-- Process psw_reg
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--
|
--
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-- Purpose:
|
-- Purpose:
|
-- Implements the PSW register.
|
-- Implements the PSW register.
|
--
|
--
|
psw_reg: process (res_i, clk_i)
|
psw_reg: process (res_i, clk_i)
|
begin
|
begin
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if res_i = res_active_c then
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if res_i = res_active_c then
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psw_q <= (others => '0');
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psw_q <= (others => '0');
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sp_q <= (others => '0');
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sp_q <= (others => '0');
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|
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elsif clk_i'event and clk_i = clk_active_c then
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elsif clk_i'event and clk_i = clk_active_c then
|
if en_clk_i then
|
if en_clk_i then
|
|
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-- T48 bus access
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-- T48 bus access
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if write_psw_i then
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if write_psw_i then
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psw_q <= data_i(7 downto 4);
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psw_q <= data_i(7 downto 4);
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end if;
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end if;
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if write_sp_i then
|
if write_sp_i then
|
sp_q <= unsigned(data_i(2 downto 0));
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sp_q <= unsigned(data_i(2 downto 0));
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end if;
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end if;
|
|
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-- increment Stack Pointer
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-- increment Stack Pointer
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if inc_stackp_i then
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if inc_stackp_i then
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sp_q <= sp_q + 1;
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sp_q <= sp_q + 1;
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end if;
|
end if;
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-- decrement Stack Pointer
|
-- decrement Stack Pointer
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if dec_stackp_i then
|
if dec_stackp_i then
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sp_q <= sp_q - 1;
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sp_q <= sp_q - 1;
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end if;
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end if;
|
|
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-- access to special bits
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-- access to special bits
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if write_carry_i then
|
if write_carry_i then
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psw_q(carry_c) <= special_data_i;
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psw_q(carry_c) <= special_data_i;
|
end if;
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end if;
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--
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--
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if write_aux_carry_i then
|
if write_aux_carry_i then
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psw_q(aux_carry_c) <= aux_carry_i;
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psw_q(aux_carry_c) <= aux_carry_i;
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end if;
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end if;
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--
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--
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if write_f0_i then
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if write_f0_i then
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psw_q(f0_c) <= special_data_i;
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psw_q(f0_c) <= special_data_i;
|
end if;
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end if;
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--
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--
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if write_bs_i then
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if write_bs_i then
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psw_q(bs_c) <= special_data_i;
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psw_q(bs_c) <= special_data_i;
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end if;
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end if;
|
|
|
end if;
|
end if;
|
|
|
end if;
|
end if;
|
|
|
end process psw_reg;
|
end process psw_reg;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Process data_out
|
-- Process data_out
|
--
|
--
|
-- Purpose:
|
-- Purpose:
|
-- Output multiplexer for T48 Data Bus.
|
-- Output multiplexer for T48 Data Bus.
|
--
|
--
|
data_out: process (read_psw_i,
|
data_out: process (read_psw_i,
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read_sp_i,
|
read_sp_i,
|
psw_q,
|
psw_q,
|
sp_q)
|
sp_q)
|
begin
|
begin
|
data_o <= (others => bus_idle_level_c);
|
data_o <= (others => bus_idle_level_c);
|
|
|
if read_psw_i then
|
if read_psw_i then
|
data_o(7 downto 4) <= psw_q;
|
data_o(7 downto 4) <= psw_q;
|
end if;
|
end if;
|
|
|
if read_sp_i then
|
if read_sp_i then
|
data_o(3 downto 0) <= '1' & conv_std_logic_vector(sp_q, 3);
|
data_o(3 downto 0) <= '1' & conv_std_logic_vector(sp_q, 3);
|
end if;
|
end if;
|
|
|
end process data_out;
|
end process data_out;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-- pragma translate_off
|
-- pragma translate_off
|
tb: process (psw_q, sp_q)
|
tb: process (psw_q, sp_q)
|
begin
|
begin
|
psw_s(7 downto 4) <= psw_q;
|
psw_s(7 downto 4) <= psw_q;
|
psw_s(3) <= '1';
|
psw_s(3) <= '1';
|
psw_s(2 downto 0) <= conv_std_logic_vector(sp_q, 3);
|
psw_s(2 downto 0) <= conv_std_logic_vector(sp_q, 3);
|
end process tb;
|
end process tb;
|
-- pragma translate_on
|
-- pragma translate_on
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Output mapping.
|
-- Output mapping.
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
carry_o <= psw_q(carry_c);
|
carry_o <= psw_q(carry_c);
|
aux_carry_o <= psw_q(aux_carry_c);
|
aux_carry_o <= psw_q(aux_carry_c);
|
f0_o <= psw_q(f0_c);
|
f0_o <= psw_q(f0_c);
|
bs_o <= psw_q(bs_c);
|
bs_o <= psw_q(bs_c);
|
|
|
-- pragma translate_off
|
|
-- workaround for GHDL 0.11
|
|
dummy_s <= '0';
|
|
-- pragma translate_on
|
|
|
|
end rtl;
|
end rtl;
|
|
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File History:
|
-- File History:
|
--
|
--
|
-- $Log: not supported by cvs2svn $
|
-- $Log: not supported by cvs2svn $
|
|
-- Revision 1.4 2004/04/18 18:59:01 arniml
|
|
-- add temporary workaround for GHDL 0.11
|
|
--
|
-- Revision 1.3 2004/04/04 14:15:45 arniml
|
-- Revision 1.3 2004/04/04 14:15:45 arniml
|
-- add dump_compare support
|
-- add dump_compare support
|
--
|
--
|
-- Revision 1.2 2004/03/28 21:28:13 arniml
|
-- Revision 1.2 2004/03/28 21:28:13 arniml
|
-- take auxiliary carry from direct ALU connection
|
-- take auxiliary carry from direct ALU connection
|
--
|
--
|
-- Revision 1.1 2004/03/23 21:31:53 arniml
|
-- Revision 1.1 2004/03/23 21:31:53 arniml
|
-- initial check-in
|
-- initial check-in
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|