OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [sim/] [rtl_sim/] [Makefile.hier] - Diff between revs 218 and 232

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##############################################################################
 
##############################################################################
 
#
 
#
 
# Core Makefile for the T48 project.
 
# Core Makefile for the T48 project.
 
#
 
#
 
# The dependencies for all VHDL source files are stored here.
 
# The dependencies for all VHDL source files are stored here.
 
# Include this file from within the tool-specific Makefile. See
 
# Include this file from within the tool-specific Makefile. See
 
# Makefile.ghdl for an example how to use it.
 
# Makefile.ghdl for an example how to use it.
 
#
 
#
 
# The following environment/make variables are expected. Set them in the
 
# The following environment/make variables are expected. Set them in the
 
# tool-specific Makefile or from the shell.
 
# tool-specific Makefile or from the shell.
 
#
 
#
 
#  PROJECT_DIR : Project base directory
 
#  PROJECT_DIR : Project base directory
 
#                Set in sw/init_project.sh
 
#                Set in sw/init_project.sh
 
#
 
#
 
#  LIB_WORK    : object directory for the work library
 
#  LIB_WORK    : object directory for the work library
 
#                /t48/sim/rtl_sim/
 
#                /t48/sim/rtl_sim/
 
#
 
#
 
#  MAKE_LIB    : command to create the work library
 
#  MAKE_LIB    : command to create the work library
 
#
 
#
 
#  ANALYZE     : command calling the tool-specific compiler for analysis of
 
#  ANALYZE     : command calling the tool-specific compiler for analysis of
 
#                the VHDL code
 
#                the VHDL code
 
#
 
#
 
#  CLEAN       : command to clean the tool-object directory
 
#  CLEAN       : command to clean the tool-object directory
 
#
 
#
 
#  Various VHDL design units.
 
#  Various VHDL design units.
 
#
 
#
 
#
 
#
 
# Copyright (c) 2004-2006, Arnim Laeuger (arniml@opencores.org)
 
# Copyright (c) 2004-2006, Arnim Laeuger (arniml@opencores.org)
 
#
 
#
 
# All rights reserved
 
# All rights reserved
 
#
 
#
 
##############################################################################
 
##############################################################################
 
RTL_DIR   = $(PROJECT_DIR)/rtl/vhdl
 
RTL_DIR   = $(PROJECT_DIR)/rtl/vhdl
 
BENCH_DIR = $(PROJECT_DIR)/bench/vhdl
 
BENCH_DIR = $(PROJECT_DIR)/bench/vhdl
 
$(LIB_WORK):
 
$(LIB_WORK):
 
        $(MAKE_LIB)
 
        $(MAKE_LIB)
 
.PHONY: clean
 
.PHONY: clean
 
clean:
 
clean:
 
        $(CLEAN); \
 
        $(CLEAN); \
 
        rm -rf *~
 
        rm -rf *~
 
.PHONY: analyze
 
.PHONY: analyze
 
analyze: $(LIB_WORK) $(tb_behav_c0) $(tb_t8048_behav_c0)
 
analyze: $(LIB_WORK) $(tb_behav_c0) $(tb_t8048_behav_c0)
 
$(alu) : $(RTL_DIR)/alu.vhd \
 
$(alu) : $(RTL_DIR)/alu.vhd   \
 
                $(alu_pack) \
 
                $(alu_pack)   \
 
                $(t48_pack) \
 
                $(t48_pack)   \
 
                $(t48_tb_pack)
 
                $(t48_tb_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(alu_pack) : $(RTL_DIR)/alu_pack-p.vhd \
 
$(alu_pack) : $(RTL_DIR)/alu_pack-p.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(alu_rtl_c0) : $(RTL_DIR)/alu-c.vhd \
 
$(alu_rtl_c0) : $(RTL_DIR)/alu-c.vhd \
 
                $(alu)
 
                $(alu)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(bus_mux) : $(RTL_DIR)/bus_mux.vhd \
 
$(bus_mux) : $(RTL_DIR)/bus_mux.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(bus_mux_rtl_c0) : $(RTL_DIR)/bus_mux-c.vhd \
 
$(bus_mux_rtl_c0) : $(RTL_DIR)/bus_mux-c.vhd \
 
                $(bus_mux-rtl) \
 
                $(bus_mux-rtl)               \
 
                $(bus_mux)
 
                $(bus_mux)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(clock_ctrl) : $(RTL_DIR)/clock_ctrl.vhd \
 
$(clock_ctrl) : $(RTL_DIR)/clock_ctrl.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(clock_ctrl_rtl_c0) : $(RTL_DIR)/clock_ctrl-c.vhd \
 
$(clock_ctrl_rtl_c0) : $(RTL_DIR)/clock_ctrl-c.vhd \
 
                $(clock_ctrl)
 
                $(clock_ctrl)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(cond_branch) : $(RTL_DIR)/cond_branch.vhd \
 
$(cond_branch) : $(RTL_DIR)/cond_branch.vhd \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack)         \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(cond_branch_pack) : $(RTL_DIR)/cond_branch_pack-p.vhd
 
$(cond_branch_pack) : $(RTL_DIR)/cond_branch_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(cond_branch_rtl_c0) : $(RTL_DIR)/cond_branch-c.vhd \
 
$(cond_branch_rtl_c0) : $(RTL_DIR)/cond_branch-c.vhd \
 
                $(cond_branch)
 
                $(cond_branch)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(db_bus) : $(RTL_DIR)/db_bus.vhd \
 
$(db_bus) : $(RTL_DIR)/db_bus.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(db_bus_rtl_c0) : $(RTL_DIR)/db_bus-c.vhd \
 
$(db_bus_rtl_c0) : $(RTL_DIR)/db_bus-c.vhd \
 
                $(db_bus)
 
                $(db_bus)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(decoder) : $(RTL_DIR)/decoder.vhd \
 
$(decoder) : $(RTL_DIR)/decoder.vhd \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)   \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)   \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack) \
 
                $(alu_pack) \
 
                $(alu_pack)         \
 
                $(t48_pack) \
 
                $(t48_pack)         \
 
                $(t48_comp_pack) \
 
                $(t48_comp_pack)    \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack)      \
 
                $(decoder_pack)
 
                $(decoder_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd
 
$(decoder_pack) : $(RTL_DIR)/decoder_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \
 
$(decoder_rtl_c0) : $(RTL_DIR)/decoder-c.vhd \
 
                $(opc_decoder_rtl_c0) \
 
                $(opc_decoder_rtl_c0)        \
 
                $(int_rtl_c0) \
 
                $(int_rtl_c0)                \
 
                $(decoder)
 
                $(decoder)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(dmem_ctrl) : $(RTL_DIR)/dmem_ctrl.vhd \
 
$(dmem_ctrl) : $(RTL_DIR)/dmem_ctrl.vhd \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)       \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(dmem_ctrl_pack) : $(RTL_DIR)/dmem_ctrl_pack-p.vhd
 
$(dmem_ctrl_pack) : $(RTL_DIR)/dmem_ctrl_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(dmem_ctrl_rtl_c0) : $(RTL_DIR)/dmem_ctrl-c.vhd \
 
$(dmem_ctrl_rtl_c0) : $(RTL_DIR)/dmem_ctrl-c.vhd \
 
                $(dmem_ctrl)
 
                $(dmem_ctrl)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(int) : $(RTL_DIR)/int.vhd \
 
$(int) : $(RTL_DIR)/int.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(int_rtl_c0) : $(RTL_DIR)/int-c.vhd \
 
$(int_rtl_c0) : $(RTL_DIR)/int-c.vhd \
 
                $(int)
 
                $(int)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(lpm_ram_dq) : $(RTL_DIR)/system/lpm_ram_dq.vhd
 
 
 
        $(ANALYZE) $<
 
 
 
 
 
 
 
$(lpm_rom) : $(RTL_DIR)/system/lpm_rom.vhd
 
 
 
        $(ANALYZE) $<
 
 
 
 
 
 
 
$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \
 
$(opc_decoder) : $(RTL_DIR)/opc_decoder.vhd \
 
                $(decoder_pack) \
 
                $(decoder_pack)             \
 
                $(t48_pack) \
 
                $(t48_pack)                 \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)           \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)           \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack)         \
 
                $(alu_pack) \
 
                $(alu_pack)                 \
 
                $(t48_comp_pack)
 
                $(t48_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \
 
$(opc_decoder_rtl_c0) : $(RTL_DIR)/opc_decoder-c.vhd \
 
                $(opc_table_rtl_c0) \
 
                $(opc_table_rtl_c0) \
 
                $(opc_decoder)
 
                $(opc_decoder)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(opc_table) : $(RTL_DIR)/opc_table.vhd \
 
$(opc_table) : $(RTL_DIR)/opc_table.vhd \
 
                $(decoder_pack) \
 
                $(decoder_pack)         \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \
 
$(opc_table_rtl_c0) : $(RTL_DIR)/opc_table-c.vhd \
 
                $(opc_table)
 
                $(opc_table)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(p1) : $(RTL_DIR)/p1.vhd \
 
$(p1) : $(RTL_DIR)/p1.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(p1_rtl_c0) : $(RTL_DIR)/p1-c.vhd \
 
$(p1_rtl_c0) : $(RTL_DIR)/p1-c.vhd \
 
                $(p1)
 
                $(p1)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(p2) : $(RTL_DIR)/p2.vhd \
 
$(p2) : $(RTL_DIR)/p2.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(p2_rtl_c0) : $(RTL_DIR)/p2-c.vhd \
 
$(p2_rtl_c0) : $(RTL_DIR)/p2-c.vhd \
 
                $(p2)
 
                $(p2)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(pmem_ctrl) : $(RTL_DIR)/pmem_ctrl.vhd \
 
$(pmem_ctrl) : $(RTL_DIR)/pmem_ctrl.vhd \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)       \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(pmem_ctrl_pack) : $(RTL_DIR)/pmem_ctrl_pack-p.vhd
 
$(pmem_ctrl_pack) : $(RTL_DIR)/pmem_ctrl_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(pmem_ctrl_rtl_c0) : $(RTL_DIR)/pmem_ctrl-c.vhd \
 
$(pmem_ctrl_rtl_c0) : $(RTL_DIR)/pmem_ctrl-c.vhd \
 
                $(pmem_ctrl)
 
                $(pmem_ctrl)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(psw) : $(RTL_DIR)/psw.vhd \
 
$(psw) : $(RTL_DIR)/psw.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(psw_rtl_c0) : $(RTL_DIR)/psw-c.vhd \
 
$(psw_rtl_c0) : $(RTL_DIR)/psw-c.vhd \
 
                $(psw)
 
                $(psw)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(syn_ram) : $(RTL_DIR)/system/syn_ram-e.vhd
 
$(lpm_ram_dq) : $(RTL_DIR)/system/lpm_ram_dq.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(syn_ram-lpm-a) : $(RTL_DIR)/system/syn_ram-lpm-a.vhd \
 
$(generic_ram_ena) : $(RTL_DIR)/system/generic_ram_ena.vhd
 
                $(syn_ram)
 
 
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
$(generic_ram_ena_rtl_c0) : $(RTL_DIR)/system/generic_ram_ena-c.vhd \
 
$(syn_ram_lpm_c0) : $(RTL_DIR)/system/syn_ram-lpm-c.vhd \
 
                            $(generic_ram_ena)
 
                $(lpm_ram_dq) \
 
 
 
                $(syn_ram-lpm-a)
 
 
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(syn_rom) : $(RTL_DIR)/system/syn_rom-e.vhd
 
$(lpm_rom) : $(RTL_DIR)/system/lpm_rom.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(syn_rom-lpm-a) : $(RTL_DIR)/system/syn_rom-lpm-a.vhd \
 
$(t48_rom) : $(RTL_DIR)/system/t48_rom-e.vhd
 
                $(syn_rom)
 
        $(ANALYZE) $<
 
 
 
$(t48_rom_lpm_a) : $(BENCH_DIR)/t48_rom-lpm-a.vhd \
 
 
 
                   $(t48_rom)
 
 
 
        $(ANALYZE) $<
 
 
 
$(t48_rom_lpm_c0) : $(BENCH_DIR)/t48_rom-lpm-c.vhd \
 
 
 
                    $(lpm_rom)                     \
 
 
 
                    $(t48_rom_lpm_a)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 
 
$(syn_rom_lpm_c0) : $(RTL_DIR)/system/syn_rom-lpm-c.vhd \
 
$(t49_rom) : $(RTL_DIR)/system/t49_rom-e.vhd
 
 
 
        $(ANALYZE) $<
 
 
 
$(t49_rom_lpm_a) : $(BENCH_DIR)/t49_rom-lpm-a.vhd \
 
 
 
                   $(t49_rom)
 
 
 
        $(ANALYZE) $<
 
 
 
$(t49_rom_lpm_c0) : $(BENCH_DIR)/t49_rom-lpm-c.vhd \
 
                $(lpm_rom) \
 
                $(lpm_rom) \
 
                $(syn_rom-lpm-a)
 
                    $(t49_rom_lpm_a)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_comp_pack) : $(RTL_DIR)/t48_comp_pack-p.vhd \
 
$(t48_comp_pack) : $(RTL_DIR)/t48_comp_pack-p.vhd \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)                 \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)                 \
 
                $(decoder_pack) \
 
                $(decoder_pack)                   \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack)               \
 
                $(t48_pack) \
 
                $(t48_pack)                       \
 
                $(alu_pack)
 
                $(alu_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_core) : $(RTL_DIR)/t48_core.vhd \
 
$(t48_core) : $(RTL_DIR)/t48_core.vhd \
 
                $(decoder_pack) \
 
                $(decoder_pack)       \
 
                $(t48_comp_pack) \
 
                $(t48_comp_pack)      \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)     \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)     \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack)   \
 
                $(t48_pack) \
 
                $(t48_pack)           \
 
                $(alu_pack)
 
                $(alu_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_core_comp_pack) : $(RTL_DIR)/t48_core_comp_pack-p.vhd
 
$(t48_core_comp_pack) : $(RTL_DIR)/t48_core_comp_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_core_struct_c0) : $(RTL_DIR)/t48_core-c.vhd \
 
$(t48_core_struct_c0) : $(RTL_DIR)/t48_core-c.vhd \
 
                $(psw_rtl_c0) \
 
                $(psw_rtl_c0)                     \
 
                $(pmem_ctrl_rtl_c0) \
 
                $(pmem_ctrl_rtl_c0)               \
 
                $(p2_rtl_c0) \
 
                $(p2_rtl_c0)                      \
 
                $(p1_rtl_c0) \
 
                $(p1_rtl_c0)                      \
 
                $(timer_rtl_c0) \
 
                $(timer_rtl_c0)                   \
 
                $(dmem_ctrl_rtl_c0) \
 
                $(dmem_ctrl_rtl_c0)               \
 
                $(decoder_rtl_c0) \
 
                $(decoder_rtl_c0)                 \
 
                $(db_bus_rtl_c0) \
 
                $(db_bus_rtl_c0)                  \
 
                $(cond_branch_rtl_c0) \
 
                $(cond_branch_rtl_c0)             \
 
                $(clock_ctrl_rtl_c0) \
 
                $(clock_ctrl_rtl_c0)              \
 
                $(bus_mux_rtl_c0) \
 
                $(bus_mux_rtl_c0)                 \
 
                $(alu_rtl_c0) \
 
                $(alu_rtl_c0)                     \
 
                $(decoder_pack) \
 
                $(decoder_pack)                   \
 
                $(t48_comp_pack) \
 
                $(t48_comp_pack)                  \
 
                $(pmem_ctrl_pack) \
 
                $(pmem_ctrl_pack)                 \
 
                $(dmem_ctrl_pack) \
 
                $(dmem_ctrl_pack)                 \
 
                $(cond_branch_pack) \
 
                $(cond_branch_pack)               \
 
                $(t48_pack) \
 
                $(t48_pack)                       \
 
                $(alu_pack) \
 
                $(alu_pack)                       \
 
                $(t48_core-struct) \
 
                $(t48_core-struct)                \
 
                $(t48_core)
 
                $(t48_core)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_pack) : $(RTL_DIR)/t48_pack-p.vhd
 
$(t48_pack) : $(RTL_DIR)/t48_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_tb_pack) : $(RTL_DIR)/t48_tb_pack-p.vhd
 
$(t48_tb_pack) : $(RTL_DIR)/t48_tb_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8048_notri) : $(RTL_DIR)/system/t8048_notri.vhd \
 
$(t8048_notri) : $(RTL_DIR)/system/t8048_notri.vhd \
 
                $(t48_core_comp_pack)
 
                $(t48_core_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8048_notri_struct_c0) : $(RTL_DIR)/system/t8048_notri-c.vhd \
 
$(t8048_notri_struct_c0) : $(RTL_DIR)/system/t8048_notri-c.vhd \
 
                $(t48_core_struct_c0) \
 
                $(t48_core_struct_c0) \
 
                $(syn_ram_lpm_c0) \
 
                $(generic_ram_ena_rtl_c0)                      \
 
                $(syn_rom_lpm_c0) \
 
                $(t48_rom_lpm_c0)                              \
 
                $(t48_core_comp_pack) \
 
                $(t48_core_comp_pack) \
 
                $(t8048_notri)
 
                $(t8048_notri)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t48_system_comp_pack) : $(RTL_DIR)/system/t48_system_comp_pack-p.vhd
 
$(t48_system_comp_pack) : $(RTL_DIR)/system/t48_system_comp_pack-p.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8048) : $(RTL_DIR)/system/t8048.vhd \
 
$(t8048) : $(RTL_DIR)/system/t8048.vhd \
 
                $(t48_system_comp_pack)
 
                $(t48_system_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8048_struct_c0) : $(RTL_DIR)/system/t8048-c.vhd \
 
$(t8048_struct_c0) : $(RTL_DIR)/system/t8048-c.vhd \
 
                $(t8048_notri_struct_c0) \
 
                $(t8048_notri_struct_c0)           \
 
                $(t8048)
 
                $(t8048)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8039_notri) : $(RTL_DIR)/system/t8039_notri.vhd \
 
$(t8039_notri) : $(RTL_DIR)/system/t8039_notri.vhd \
 
                $(t48_core_comp_pack)
 
                $(t48_core_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8039_notri_struct_c0) : $(RTL_DIR)/system/t8039_notri-c.vhd \
 
$(t8039_notri_struct_c0) : $(RTL_DIR)/system/t8039_notri-c.vhd \
 
                $(t48_core_struct_c0) \
 
                $(t48_core_struct_c0) \
 
                $(syn_ram_lpm_c0) \
 
                $(generic_ram_ena_rtl_c0)                      \
 
                $(t8039_notri)
 
                $(t8039_notri)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8039) : $(RTL_DIR)/system/t8039.vhd \
 
$(t8039) : $(RTL_DIR)/system/t8039.vhd \
 
                $(t48_system_comp_pack)
 
                $(t48_system_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(t8039_struct_c0) : $(RTL_DIR)/system/t8039-c.vhd \
 
$(t8039_struct_c0) : $(RTL_DIR)/system/t8039-c.vhd \
 
                $(t8039_notri_struct_c0) \
 
                $(t8039_notri_struct_c0)           \
 
                $(t8039)
 
                $(t8039)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(if_timing) : $(BENCH_DIR)/if_timing.vhd
 
$(if_timing) : $(BENCH_DIR)/if_timing.vhd
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(if_timing_behav_c0) : $(BENCH_DIR)/if_timing-c.vhd \
 
$(if_timing_behav_c0) : $(BENCH_DIR)/if_timing-c.vhd \
 
                $(if_timing)
 
                $(if_timing)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb) : $(BENCH_DIR)/tb.vhd \
 
$(tb) : $(BENCH_DIR)/tb.vhd           \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack)        \
 
                $(t48_core_comp_pack)
 
                $(t48_core_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb_behav_c0) : $(BENCH_DIR)/tb-c.vhd \
 
$(tb_behav_c0) : $(BENCH_DIR)/tb-c.vhd    \
 
                $(if_timing_behav_c0) \
 
                $(if_timing_behav_c0)     \
 
                $(t48_core_struct_c0) \
 
                $(t48_core_struct_c0) \
 
                $(syn_ram_lpm_c0) \
 
                $(generic_ram_ena_rtl_c0) \
 
                $(lpm_rom) \
 
                $(lpm_rom) \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack)            \
 
                $(t48_core_comp_pack) \
 
                $(t48_core_comp_pack)     \
 
                $(tb-behav) \
 
                $(tb-behav)               \
 
                $(tb)
 
                $(tb)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb_t8039) : $(BENCH_DIR)/tb_t8039.vhd \
 
$(tb_t8039) : $(BENCH_DIR)/tb_t8039.vhd \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack)          \
 
                $(t48_core_comp_pack)
 
                $(t48_core_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb_t8039_behav_c0) : $(BENCH_DIR)/tb_t8039-c.vhd \
 
$(tb_t8039_behav_c0) : $(BENCH_DIR)/tb_t8039-c.vhd \
 
                $(t8039_struct_c0) \
 
                $(t8039_struct_c0) \
 
                $(syn_ram_lpm_c0) \
 
                $(generic_ram_rtl_c0)              \
 
                $(syn_rom_lpm_c0) \
 
                $(lpm_rom)                         \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack) \
 
                $(t48_core_comp_pack) \
 
                $(t48_core_comp_pack) \
 
 
 
                $(t48_system_comp_pack)            \
 
                $(tb_t8039)
 
                $(tb_t8039)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb_t8048) : $(BENCH_DIR)/tb_t8048.vhd \
 
$(tb_t8048) : $(BENCH_DIR)/tb_t8048.vhd \
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack)          \
 
                $(t48_core_comp_pack)
 
                $(t48_core_comp_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(tb_t8048_behav_c0) : $(BENCH_DIR)/tb_t8048-c.vhd \
 
$(tb_t8048_behav_c0) : $(BENCH_DIR)/tb_t8048-c.vhd \
 
                $(t8048_struct_c0) \
 
                $(t8048_struct_c0) \
 
                $(syn_ram_lpm_c0) \
 
                $(generic_ram_ena_rtl_c0)          \
 
                $(syn_rom_lpm_c0) \
 
 
 
                $(t48_tb_pack) \
 
                $(t48_tb_pack) \
 
                $(t48_core_comp_pack) \
 
                $(t48_core_comp_pack)              \
 
                $(tb_t8048)
 
                $(tb_t8048)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(timer) : $(RTL_DIR)/timer.vhd \
 
$(timer) : $(RTL_DIR)/timer.vhd \
 
                $(t48_pack)
 
                $(t48_pack)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
$(timer_rtl_c0) : $(RTL_DIR)/timer-c.vhd \
 
$(timer_rtl_c0) : $(RTL_DIR)/timer-c.vhd \
 
                $(timer-rtl) \
 
                $(timer-rtl)             \
 
                $(t48_pack) \
 
                $(t48_pack)              \
 
                $(timer)
 
                $(timer)
 
        $(ANALYZE) $<
 
        $(ANALYZE) $<
 
 
 
 

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