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Change log for the T48 uController core
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Change log for the T48 uController core
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=======================================
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=======================================
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Version: $Date: 2008-04-30 22:45:44 $
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Version: $Date: 2008-04-30 22:45:44 $
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$Name: not supported by cvs2svn $
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$Name: not supported by cvs2svn $
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Release 1.1
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Release 1.1
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* code optimizations in the decoder to reduce LUT usage with
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* code optimizations in the decoder to reduce LUT usage with
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Xilinx ISE/XST.
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Xilinx ISE/XST.
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* fix tb_t8048 and tb_t8049 with respect to P1[0]->T0 signalling.
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* fix tb_t8048 and tb_t8049 with respect to P1[0]->T0 signalling.
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* synthesis templates for QuartusII and ISE.
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* synthesis templates for QuartusII and ISE.
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* added dedicated version of hex2rom utility for RTL ROM generation
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* added dedicated version of hex2rom utility for RTL ROM generation
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(keeps compatibility with QuartusII 7.2).
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(keeps compatibility with QuartusII 7.2).
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* better describe RTL ROM and RAM macros.
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* better describe RTL ROM and RAM macros.
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Release 1.0
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Release 1.0
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* T8243 I/O expander added to project
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* T8243 I/O expander added to project
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* Bugfix for "Deassertion of PROG too early"
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* Bugfix for "Deassertion of PROG too early"
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PROG is deasserted at end of XTAL3 now.
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PROG is deasserted at end of XTAL3 now.
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Applied in clock_ctrl.vhd 1.12
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Applied in clock_ctrl.vhd 1.12
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* new input xtal_en_i gates xtal_i base clock
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* new input xtal_en_i gates xtal_i base clock
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* counter_q in timer module has asynchronous reset
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* counter_q in timer module has asynchronous reset
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* replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
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* replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
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* verification environment updated for new testbenches
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* verification environment updated for new testbenches
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Release 0.6.1 BETA
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Release 0.6.1 BETA
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------------------
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* Bugfix for "PROBLEM WHEN INT AND JMP"
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* Bugfix for "PROBLEM WHEN INT AND JMP"
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Suppress assertion of bus_read_bus_s when interrupt is pending.
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Suppress assertion of bus_read_bus_s when interrupt is pending.
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Applied in decoder.vhd 1.21
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Applied in decoder.vhd 1.21
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* Bugfix for "P2 Port value restored after expander access"
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* Bugfix for "P2 Port value restored after expander access"
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Applied in p2.vhd 1.8
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Applied in p2.vhd 1.8
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* change low impedance markers for P2
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* change low impedance markers for P2
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separate marker for low and high part
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separate marker for low and high part
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* shift assertion of ALE and PROG to xtal3
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* shift assertion of ALE and PROG to xtal3
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* properly drive P1 and P2 with low impedance markers
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* properly drive P1 and P2 with low impedance markers
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* suppress p2_output_pch_o when MOVX operation is accessing the
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* suppress p2_output_pch_o when MOVX operation is accessing the
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external memory
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external memory
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* suppress p2_output_pch_o when p2_output_exp is active
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* suppress p2_output_pch_o when p2_output_exp is active
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* operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3
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* operate ale_q and int_q with xtal_i after shift of ALE assertion to XTAL3
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Release 0.6 BETA
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Release 0.6 BETA
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* Bugfix for "Wrong clock applied to T0"
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* Bugfix for "Wrong clock applied to T0"
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Applied in clock_ctrl.vhd 1.7
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Applied in clock_ctrl.vhd 1.7
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t48_core.vhd 1.8
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t48_core.vhd 1.8
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* Introduced "notri" hierarchy for t8048 and t8039 system.
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* Introduced "notri" hierarchy for t8048 and t8039 system.
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This allows the usage of such a system without tri-state signals.
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This allows the usage of such a system without tri-state signals.
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* Fixed lpm_memory type definition in lpm_rom.vhd and lpm_ram.vhd.
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* Fixed lpm_memory type definition in lpm_rom.vhd and lpm_ram.vhd.
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* New Wishbone master module: wb_master.vhd
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* New Wishbone master module: wb_master.vhd
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* New system toplevel: t8050_wb.vhd
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* New system toplevel: t8050_wb.vhd
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Contains the Wishbone master.
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Contains the Wishbone master.
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* Prefixed all design units with 't48_'.
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* Prefixed all design units with 't48_'.
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* Updates for running the core with full xtal clock. Should work now.
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* Updates for running the core with full xtal clock. Should work now.
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* Move latching of BUS to MSTATE2 in decoder.vhd
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* Move latching of BUS to MSTATE2 in decoder.vhd
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-> sample BUS at the end of RD'
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-> sample BUS at the end of RD'
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* Fix a glitch on PCH when an interrupt occurs during external
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* Fix a glitch on PCH when an interrupt occurs during external
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program memory fetch in decoder.vhd
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program memory fetch in decoder.vhd
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* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted
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* Bugfix for "Target address of JMP to Program Memory Bank 1 corrupted
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by interrupt"
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by interrupt"
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and "Return address of CALL to Program Memory Bank 1 corrupted
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and "Return address of CALL to Program Memory Bank 1 corrupted
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by interrupt"
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by interrupt"
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Applied in int.vhd 1.5
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Applied in int.vhd 1.5
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* Bugfix for "MSB of Program Counter changed upon PC increment"
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* Bugfix for "MSB of Program Counter changed upon PC increment"
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Applied in pmem_ctrl.vhd 1.4
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Applied in pmem_ctrl.vhd 1.4
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* Preliminary Integration Manual added.
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* Preliminary Integration Manual added.
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Release 0.5 BETA
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Release 0.5 BETA
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* Bugfix for "P1 constantly in push-pull mode in t8048"
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* Bugfix for "P1 constantly in push-pull mode in t8048"
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Applied in t8048.vhd 1.3
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Applied in t8048.vhd 1.3
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* Bugfix for "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
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* Bugfix for "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
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Applied in decoder.vhd 1.16
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Applied in decoder.vhd 1.16
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db_bus.vhd 1.3
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db_bus.vhd 1.3
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Updated testcase black_box/ins.
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Updated testcase black_box/ins.
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* P1, P2 and BUS are written during the first instruction cycle of the
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* P1, P2 and BUS are written during the first instruction cycle of the
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OUTL instruction. This matches the descirption in the User Manual.
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OUTL instruction. This matches the descirption in the User Manual.
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The previous implementation updated these ports at the end of the
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The previous implementation updated these ports at the end of the
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second instruction cycle.
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second instruction cycle.
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Applied in decoder.vhd 1.16
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Applied in decoder.vhd 1.16
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* Shifted deassertion of RD and WR to end of XTAL3 of machine state 2.
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* Shifted deassertion of RD and WR to end of XTAL3 of machine state 2.
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The previous deassertion at the end of XTAL2 was not according to the
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The previous deassertion at the end of XTAL2 was not according to the
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User Manual. Their rising edge can now be used as a read/write strobe.
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User Manual. Their rising edge can now be used as a read/write strobe.
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On the other hand, PROG is still deasserted at the end of XTAL3. This
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On the other hand, PROG is still deasserted at the end of XTAL3. This
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is needed to for the rising edge of PROG within valid P2 expander data.
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is needed to for the rising edge of PROG within valid P2 expander data.
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Applied in clock_ctrl.vhd 1.6
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Applied in clock_ctrl.vhd 1.6
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