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;; *******************************************************************
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;; *******************************************************************
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;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
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;; $Id: test.asm,v 1.1.1.1 2004-03-25 22:29:17 arniml Exp $
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;;
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;;
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;; Test ANL A, @ Rr.
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;; Test ANL A, @ Rr.
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;; *******************************************************************
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;; *******************************************************************
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INCLUDE "cpu.inc"
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INCLUDE "cpu.inc"
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INCLUDE "pass_fail.inc"
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INCLUDE "pass_fail.inc"
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testR0R1 MACRO pos
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testR0R1 MACRO pos
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #(1 << pos)
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mov a, #(1 << pos)
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anl a, @r0
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anl a, @r0
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jnz fail
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jnz fail
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mov a, #0FFH
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mov a, #0FFH
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anl a, @r0
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anl a, @r0
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add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
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add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
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jnz fail
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jnz fail
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mov a, #(1 << pos)
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mov a, #(1 << pos)
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anl a, @r1
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anl a, @r1
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jnz fail
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jnz fail
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mov a, #0FFH
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mov a, #0FFH
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anl a, @r1
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anl a, @r1
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add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
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add a, #(~(0FFH - (1 << pos)) + 1) & 0FFH
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jnz fail
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jnz fail
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ENDM
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ENDM
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ORG 0
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ORG 0
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;; Start of test
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;; Start of test
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mov r0, #010H
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mov r0, #010H
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mov r1, #020H
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mov r1, #020H
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mov a, #0FEH
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mov a, #0FEH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0FDH
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mov a, #0FDH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0FBH
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mov a, #0FBH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0F7H
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mov a, #0F7H
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0EFH
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mov a, #0EFH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0DFH
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mov a, #0DFH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #0BFH
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mov a, #0BFH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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inc r0
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inc r0
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inc r1
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inc r1
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mov a, #07FH
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mov a, #07FH
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mov @r0, a
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mov @r0, a
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mov @r1, a
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mov @r1, a
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jmp goon
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jmp goon
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ORG 256
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ORG 256
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;;
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;;
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goon: mov r0, #00FH
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goon: mov r0, #00FH
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mov r1, #01FH
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mov r1, #01FH
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testR0R1 0
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testR0R1 0
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testR0R1 1
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testR0R1 1
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testR0R1 2
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testR0R1 2
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testR0R1 3
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testR0R1 3
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testR0R1 4
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testR0R1 4
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testR0R1 5
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testR0R1 5
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testR0R1 6
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testR0R1 6
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testR0R1 7
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testR0R1 7
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pass: PASS
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pass: PASS
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fail: FAIL
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fail: FAIL
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