-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
--
|
--
|
-- The testbench for t8048.
|
-- The testbench for t8048.
|
--
|
--
|
-- $Id: tb_t8048.vhd 295 2009-04-01 19:32:48Z arniml $
|
-- $Id: tb_t8048.vhd 295 2009-04-01 19:32:48Z arniml $
|
--
|
--
|
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
|
--
|
--
|
-- All rights reserved
|
-- All rights reserved
|
--
|
--
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- Redistribution and use in source and synthezised forms, with or without
|
-- modification, are permitted provided that the following conditions are met:
|
-- modification, are permitted provided that the following conditions are met:
|
--
|
--
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-- Redistributions of source code must retain the above copyright notice,
|
-- Redistributions of source code must retain the above copyright notice,
|
-- this list of conditions and the following disclaimer.
|
-- this list of conditions and the following disclaimer.
|
--
|
--
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- Redistributions in synthesized form must reproduce the above copyright
|
-- notice, this list of conditions and the following disclaimer in the
|
-- notice, this list of conditions and the following disclaimer in the
|
-- documentation and/or other materials provided with the distribution.
|
-- documentation and/or other materials provided with the distribution.
|
--
|
--
|
-- Neither the name of the author nor the names of other contributors may
|
-- Neither the name of the author nor the names of other contributors may
|
-- be used to endorse or promote products derived from this software without
|
-- be used to endorse or promote products derived from this software without
|
-- specific prior written permission.
|
-- specific prior written permission.
|
--
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--
|
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
-- POSSIBILITY OF SUCH DAMAGE.
|
-- POSSIBILITY OF SUCH DAMAGE.
|
--
|
--
|
-- Please report bugs to the author, but before you do so, please
|
-- Please report bugs to the author, but before you do so, please
|
-- make sure that this is not a derivative work and that
|
-- make sure that this is not a derivative work and that
|
-- you have the latest version of this file.
|
-- you have the latest version of this file.
|
--
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--
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-- The latest version of this file can be found at:
|
-- The latest version of this file can be found at:
|
-- http://www.opencores.org/cvsweb.shtml/t48/
|
-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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|
|
library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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|
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entity tb_t8048 is
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entity tb_t8048 is
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|
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end tb_t8048;
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end tb_t8048;
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use work.t48_core_comp_pack.generic_ram_ena;
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use work.t48_core_comp_pack.generic_ram_ena;
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use work.t48_system_comp_pack.t8048;
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use work.t48_system_comp_pack.t8048;
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|
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use work.t48_tb_pack.all;
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use work.t48_tb_pack.all;
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|
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architecture behav of tb_t8048 is
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architecture behav of tb_t8048 is
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|
|
-- clock period, 11 MHz
|
-- clock period, 11 MHz
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constant period_c : time := 90 ns;
|
constant period_c : time := 90 ns;
|
|
|
component lpm_rom
|
component lpm_rom
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generic (
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generic (
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LPM_WIDTH : positive;
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LPM_WIDTH : positive;
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LPM_TYPE : string := "LPM_ROM";
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LPM_TYPE : string := "LPM_ROM";
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LPM_WIDTHAD : positive;
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LPM_WIDTHAD : positive;
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LPM_NUMWORDS : natural := 0;
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LPM_NUMWORDS : natural := 0;
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LPM_FILE : string;
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LPM_FILE : string;
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LPM_ADDRESS_CONTROL : string := "REGISTERED";
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LPM_ADDRESS_CONTROL : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_OUTDATA : string := "REGISTERED";
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LPM_HINT : string := "UNUSED"
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LPM_HINT : string := "UNUSED"
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);
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);
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port (
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port (
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address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
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inclock : in std_logic;
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inclock : in std_logic;
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outclock : in std_logic;
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outclock : in std_logic;
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memenab : in std_logic;
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memenab : in std_logic;
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q : out std_logic_vector(LPM_WIDTH-1 downto 0)
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q : out std_logic_vector(LPM_WIDTH-1 downto 0)
|
);
|
);
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end component;
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end component;
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|
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signal xtal_s : std_logic;
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signal xtal_s : std_logic;
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signal res_n_s : std_logic;
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signal res_n_s : std_logic;
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signal int_n_s : std_logic;
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signal int_n_s : std_logic;
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signal ale_s : std_logic;
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signal ale_s : std_logic;
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signal psen_n_s : std_logic;
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signal psen_n_s : std_logic;
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signal prog_n_s : std_logic;
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signal prog_n_s : std_logic;
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|
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signal t0_b : std_logic;
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signal t0_b : std_logic;
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|
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p1_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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signal p2_b : std_logic_vector( 7 downto 0);
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|
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signal db_b : std_logic_vector( 7 downto 0);
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signal db_b : std_logic_vector( 7 downto 0);
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signal ext_mem_addr_s : std_logic_vector(11 downto 0);
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signal ext_mem_addr_s : std_logic_vector(11 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_data_from_s : std_logic_vector( 7 downto 0);
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signal ext_ram_we_s : std_logic;
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signal ext_ram_we_s : std_logic;
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signal ext_rom_data_s : std_logic_vector( 7 downto 0);
|
signal ext_rom_data_s : std_logic_vector( 7 downto 0);
|
signal rd_n_s : std_logic;
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signal rd_n_s : std_logic;
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signal wr_n_s : std_logic;
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signal wr_n_s : std_logic;
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|
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signal zero_s : std_logic;
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signal zero_s : std_logic;
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signal one_s : std_logic;
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signal one_s : std_logic;
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|
|
begin
|
begin
|
|
|
zero_s <= '0';
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zero_s <= '0';
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one_s <= '1';
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one_s <= '1';
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|
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p2_b <= (others => 'H');
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p2_b <= (others => 'H');
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p1_b <= (others => 'H');
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p1_b <= (others => 'H');
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|
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- External ROM, 3k bytes
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-- External ROM, 3k bytes
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-- Initialized by file t48_ext_rom.hex.
|
-- Initialized by file t48_ext_rom.hex.
|
-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
|
ext_rom_b : lpm_rom
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ext_rom_b : lpm_rom
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generic map (
|
generic map (
|
LPM_WIDTH => 8,
|
LPM_WIDTH => 8,
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LPM_TYPE => "LPM_ROM",
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LPM_TYPE => "LPM_ROM",
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LPM_WIDTHAD => 12,
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LPM_WIDTHAD => 12,
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LPM_NUMWORDS => 3 * (2 ** 10),
|
LPM_NUMWORDS => 3 * (2 ** 10),
|
LPM_FILE => "rom_t48_ext.hex",
|
LPM_FILE => "rom_t48_ext.hex",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_ADDRESS_CONTROL => "REGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_OUTDATA => "UNREGISTERED",
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LPM_HINT => "UNUSED"
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LPM_HINT => "UNUSED"
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)
|
)
|
port map (
|
port map (
|
address => ext_mem_addr_s,
|
address => ext_mem_addr_s,
|
inclock => xtal_s,
|
inclock => xtal_s,
|
outclock => zero_s, -- unused
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outclock => zero_s, -- unused
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memenab => one_s,
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memenab => one_s,
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q => ext_rom_data_s
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q => ext_rom_data_s
|
);
|
);
|
|
|
ext_ram_b : generic_ram_ena
|
ext_ram_b : generic_ram_ena
|
generic map (
|
generic map (
|
addr_width_g => 8,
|
addr_width_g => 8,
|
data_width_g => 8
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data_width_g => 8
|
)
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)
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port map (
|
port map (
|
clk_i => xtal_s,
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clk_i => xtal_s,
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a_i => ext_mem_addr_s(7 downto 0),
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a_i => ext_mem_addr_s(7 downto 0),
|
we_i => ext_ram_we_s,
|
we_i => ext_ram_we_s,
|
ena_i => one_s,
|
ena_i => one_s,
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d_i => db_b,
|
d_i => db_b,
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d_o => ext_ram_data_from_s
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d_o => ext_ram_data_from_s
|
);
|
);
|
|
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t8048_b : t8048
|
t8048_b : t8048
|
port map (
|
port map (
|
xtal_i => xtal_s,
|
xtal_i => xtal_s,
|
reset_n_i => res_n_s,
|
reset_n_i => res_n_s,
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t0_b => t0_b,
|
t0_b => t0_b,
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int_n_i => int_n_s,
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int_n_i => int_n_s,
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ea_i => zero_s,
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ea_i => zero_s,
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rd_n_o => rd_n_s,
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rd_n_o => rd_n_s,
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psen_n_o => psen_n_s,
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psen_n_o => psen_n_s,
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wr_n_o => wr_n_s,
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wr_n_o => wr_n_s,
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ale_o => ale_s,
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ale_o => ale_s,
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db_b => db_b,
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db_b => db_b,
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t1_i => p1_b(1),
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t1_i => p1_b(1),
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p2_b => p2_b,
|
p2_b => p2_b,
|
p1_b => p1_b,
|
p1_b => p1_b,
|
prog_n_o => prog_n_s
|
prog_n_o => prog_n_s
|
);
|
);
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Read from external memory
|
-- Read from external memory
|
--
|
--
|
db_b <= ext_rom_data_s
|
db_b <= ext_rom_data_s
|
when psen_n_s = '0' else
|
when psen_n_s = '0' else
|
(others => 'Z');
|
(others => 'Z');
|
db_b <= ext_ram_data_from_s
|
db_b <= ext_ram_data_from_s
|
when rd_n_s = '0' else
|
when rd_n_s = '0' else
|
(others => 'Z');
|
(others => 'Z');
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- External RAM access signals
|
-- External RAM access signals
|
--
|
--
|
ext_ram: process (wr_n_s,
|
ext_ram: process (wr_n_s,
|
ale_s,
|
ale_s,
|
p2_b,
|
p2_b,
|
db_b)
|
db_b)
|
begin
|
begin
|
-- lowest 1k of external ROM is not used
|
-- lowest 1k of external ROM is not used
|
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
|
ext_mem_addr_s(11 downto 8) <= To_X01Z(p2_b(3 downto 0));
|
|
|
if ale_s'event and ale_s = '0' then
|
if ale_s'event and ale_s = '0' then
|
if not is_X(db_b) then
|
if not is_X(db_b) then
|
ext_mem_addr_s(7 downto 0) <= db_b;
|
ext_mem_addr_s(7 downto 0) <= db_b;
|
else
|
else
|
ext_mem_addr_s(7 downto 0) <= (others => '0');
|
ext_mem_addr_s(7 downto 0) <= (others => '0');
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
if wr_n_s'event and wr_n_s = '1' then
|
if wr_n_s'event and wr_n_s = '1' then
|
ext_ram_we_s <= '0';
|
ext_ram_we_s <= '0';
|
end if;
|
end if;
|
if wr_n_s'event and wr_n_s = '0' then
|
if wr_n_s'event and wr_n_s = '0' then
|
ext_ram_we_s <= '1';
|
ext_ram_we_s <= '1';
|
end if;
|
end if;
|
|
|
end process ext_ram;
|
end process ext_ram;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
t0_b <= p1_b(0);
|
t0_b <= p1_b(0);
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- The clock generator
|
-- The clock generator
|
--
|
--
|
clk_gen: process
|
clk_gen: process
|
begin
|
begin
|
xtal_s <= '0';
|
xtal_s <= '0';
|
wait for period_c/2;
|
wait for period_c/2;
|
xtal_s <= '1';
|
xtal_s <= '1';
|
wait for period_c/2;
|
wait for period_c/2;
|
end process clk_gen;
|
end process clk_gen;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- The reset generator
|
-- The reset generator
|
--
|
--
|
res_gen: process
|
res_gen: process
|
begin
|
begin
|
res_n_s <= '0';
|
res_n_s <= '0';
|
wait for 5 * period_c;
|
wait for 5 * period_c;
|
res_n_s <= '1';
|
res_n_s <= '1';
|
wait;
|
wait;
|
end process res_gen;
|
end process res_gen;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- The interrupt generator
|
-- The interrupt generator
|
--
|
--
|
int_gen: process
|
int_gen: process
|
begin
|
begin
|
int_n_s <= '1';
|
int_n_s <= '1';
|
wait for 750 * period_c;
|
wait for 750 * period_c;
|
int_n_s <= '0';
|
int_n_s <= '0';
|
wait for 45 * period_c;
|
wait for 45 * period_c;
|
end process int_gen;
|
end process int_gen;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- End of simulation detection
|
-- End of simulation detection
|
--
|
--
|
eos: process
|
eos: process
|
begin
|
begin
|
|
|
outer: loop
|
outer: loop
|
wait on tb_accu_s;
|
wait on tb_accu_s;
|
if tb_accu_s = "10101010" then
|
if tb_accu_s = "10101010" then
|
wait on tb_accu_s;
|
wait on tb_accu_s;
|
if tb_accu_s = "01010101" then
|
if tb_accu_s = "01010101" then
|
wait on tb_accu_s;
|
wait on tb_accu_s;
|
if tb_accu_s = "00000001" then
|
if tb_accu_s = "00000001" then
|
-- wait for instruction strobe of this move
|
-- wait for instruction strobe of this move
|
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
|
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
|
-- wait for next strobe
|
-- wait for next strobe
|
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
|
wait until tb_istrobe_s'event and tb_istrobe_s = '1';
|
assert false
|
assert false
|
report "Simulation Result: PASS."
|
report "Simulation Result: PASS."
|
severity note;
|
severity note;
|
else
|
else
|
assert false
|
assert false
|
report "Simulation Result: FAIL."
|
report "Simulation Result: FAIL."
|
severity note;
|
severity note;
|
end if;
|
end if;
|
|
|
assert false
|
assert false
|
report "End of simulation reached."
|
report "End of simulation reached."
|
severity failure;
|
severity failure;
|
|
|
end if;
|
end if;
|
end if;
|
end if;
|
end loop;
|
end loop;
|
|
|
end process eos;
|
end process eos;
|
--
|
--
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
|
|
end behav;
|
end behav;
|
|
|