-- This file was generated with hex2rom written by Daniel Wallner
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-- This file was generated with hex2rom written by Daniel Wallner
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library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.numeric_std.all;
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entity rom_t48 is
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entity rom_t48 is
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port(
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port(
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Clk : in std_logic;
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Clk : in std_logic;
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A : in std_logic_vector(9 downto 0);
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A : in std_logic_vector(9 downto 0);
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D : out std_logic_vector(7 downto 0)
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D : out std_logic_vector(7 downto 0)
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);
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);
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end rom_t48;
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end rom_t48;
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architecture rtl of rom_t48 is
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architecture rtl of rom_t48 is
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signal A_r : std_logic_vector(9 downto 0);
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signal A_r : std_logic_vector(9 downto 0);
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begin
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begin
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process (Clk)
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process (Clk)
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begin
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begin
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if Clk'event and Clk = '1' then
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if Clk'event and Clk = '1' then
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A_r <= A;
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A_r <= A;
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end if;
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end if;
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end process;
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end process;
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process (A_r)
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process (A_r)
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begin
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begin
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case to_integer(unsigned(A_r)) is
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case to_integer(unsigned(A_r)) is
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when 000000 => D <= "00100011"; -- 0x0000
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when 000000 => D <= "00100011"; -- 0x0000
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when 000001 => D <= "11111111"; -- 0x0001
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when 000001 => D <= "11111111"; -- 0x0001
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when 000002 => D <= "00111001"; -- 0x0002
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when 000002 => D <= "00111001"; -- 0x0002
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when 000003 => D <= "11010011"; -- 0x0003
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when 000003 => D <= "11010011"; -- 0x0003
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when 000004 => D <= "00000001"; -- 0x0004
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when 000004 => D <= "00000001"; -- 0x0004
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when 000005 => D <= "00000100"; -- 0x0005
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when 000005 => D <= "00000100"; -- 0x0005
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when 000006 => D <= "00000010"; -- 0x0006
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when 000006 => D <= "00000010"; -- 0x0006
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when others => D <= "--------";
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when others => D <= "--------";
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end case;
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end case;
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end process;
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end process;
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end;
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end;
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