alu_chk.e
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alu_chk.e
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<'
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<'
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import alu_components;
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import alu_components;
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unit alu_chk_u {
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unit alu_chk_u {
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reg_a : byte;
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reg_a : byte;
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reg_x : byte;
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reg_x : byte;
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reg_y : byte;
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reg_y : byte;
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reg_status : byte;
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reg_status : byte;
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reg_result : byte;
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reg_result : byte;
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!inst : alu_input_s;
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!inst : alu_input_s;
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!next_inst : alu_input_s;
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!next_inst : alu_input_s;
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count_cycles : int;
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count_cycles : int;
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first_cycle : bool;
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first_cycle : bool;
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last_a : byte;
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last_a : byte;
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last_status : byte;
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last_status : byte;
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last_result : byte;
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last_result : byte;
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rst_counter : byte;
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rst_counter : byte;
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keep first_cycle == TRUE;
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keep first_cycle == TRUE;
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keep count_cycles == 0;
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keep count_cycles == 0;
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keep rst_counter == 0;
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keep rst_counter == 0;
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event T3_cover_event;
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event T3_cover_event;
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cover T3_cover_event is {
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cover T3_cover_event is {
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item rst_counter; // using num_of_buckets=100;
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item rst_counter; // using num_of_buckets=100;
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};
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};
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store(input : alu_input_s) is {
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store(input : alu_input_s) is {
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count_cycles = count_cycles + 1;
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count_cycles = count_cycles + 1;
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//out ("CYCLE ", count_cycles, " STORE:");
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//out ("CYCLE ", count_cycles, " STORE:");
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//print input;
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//print input;
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last_a = reg_a;
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last_a = reg_a;
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last_status = reg_status;
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last_status = reg_status;
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last_result = reg_result;
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last_result = reg_result;
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if (first_cycle) {
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if (first_cycle) {
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inst = input;
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inst = input;
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next_inst = input;
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next_inst = input;
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}
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}
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else {
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else {
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inst = next_inst;
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inst = next_inst;
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next_inst = input;
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next_inst = input;
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};
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};
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};
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};
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compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
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compare(alu_result:byte, alu_status:byte, alu_x:byte, alu_y:byte ) is {
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if (first_cycle) {
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if (first_cycle) {
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first_cycle = FALSE;
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first_cycle = FALSE;
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reg_x = 0;
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reg_x = 0;
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reg_y = 0;
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reg_y = 0;
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reg_status = 8'b00100010;
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reg_status = 8'b00100010;
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reg_a = 0;
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reg_a = 0;
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reg_result = 0;
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reg_result = 0;
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}
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}
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else {
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else {
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//out ("CYCLE ", count_cycles, " COMPARE:");
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//out ("CYCLE ", count_cycles, " COMPARE:");
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//print inst;
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//print inst;
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if (count_cycles == 99999) {
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if (count_cycles == 99999) {
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out("ENOUGH!");
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out("ENOUGH!");
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stop_run();
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stop_run();
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};
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};
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if (inst.input_kind == RESET) {
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if (inst.input_kind == RESET) {
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rst_counter = rst_counter + 1;
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rst_counter = rst_counter + 1;
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}
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}
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else {
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else {
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emit T3_cover_event;
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emit T3_cover_event;
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rst_counter = 0;
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rst_counter = 0;
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};
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};
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case inst.input_kind {
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case inst.input_kind {
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ENABLED_VALID: {
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ENABLED_VALID: {
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//out("CYCLE ", count_cycles, ": executing and comparing");
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//out("CYCLE ", count_cycles, ": executing and comparing");
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execute(inst.alu_opcode);
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execute(inst.alu_opcode);
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if (reg_status[3:3] == 1) {
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if (reg_status[3:3] == 1) {
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case inst.alu_opcode {
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case inst.alu_opcode {
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SBC_IMM: {
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SBC_IMM: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ZPG: {
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SBC_ZPG: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ZPX: {
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SBC_ZPX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABS: {
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SBC_ABS: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABX: {
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SBC_ABX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABY: {
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SBC_ABY: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_IDX: {
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SBC_IDX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_IDY: {
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SBC_IDY: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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};
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};
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};
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};
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};
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};
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RESET: {
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RESET: {
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reg_x = 0;
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reg_x = 0;
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reg_y = 0;
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reg_y = 0;
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reg_status = 8'b00100010;
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reg_status = 8'b00100010;
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reg_a = 0; // TODO: check this
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reg_a = 0; // TODO: check this
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reg_result = 0;
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reg_result = 0;
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return;
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return;
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};
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};
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ENABLED_RAND: {
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ENABLED_RAND: {
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execute(inst.rand_op.as_a(valid_opcodes));
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execute(inst.rand_op.as_a(valid_opcodes));
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if (reg_status[3:3] == 1) {
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if (reg_status[3:3] == 1) {
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case inst.rand_op.as_a(valid_opcodes) {
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case inst.rand_op.as_a(valid_opcodes) {
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SBC_IMM: {
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SBC_IMM: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ZPG: {
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SBC_ZPG: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ZPX: {
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SBC_ZPX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABS: {
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SBC_ABS: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABX: {
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SBC_ABX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_ABY: {
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SBC_ABY: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_IDX: {
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SBC_IDX: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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SBC_IDY: {
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SBC_IDY: {
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reg_a = alu_result;
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reg_a = alu_result;
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reg_result = alu_result;
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reg_result = alu_result;
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reg_status = alu_status;
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reg_status = alu_status;
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};
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};
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};
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};
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};
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};
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};
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};
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default: {
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default: {
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};
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};
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};
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};
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// here i have already calculated. must compare!
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// here i have already calculated. must compare!
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if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
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if ((reg_result != alu_result) || (reg_x != alu_x) or (reg_y != alu_y) or (reg_status != alu_status)) {
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out("#########################################################");
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out("#########################################################");
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print me;
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print me;
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print me.inst;
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print me.inst;
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out("#########################################################");
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out("#########################################################");
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print alu_result;
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print alu_result;
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print alu_status;
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print alu_status;
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print alu_x;
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print alu_x;
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print alu_y;
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print alu_y;
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dut_error("WRONG!");
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dut_error("WRONG!");
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};
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};
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};
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};
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};
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};
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execute(opcode : valid_opcodes) is {
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execute(opcode : valid_opcodes) is {
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case opcode {
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case opcode {
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ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
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ADC_IMM: { exec_sum(); }; // A,Z,C,N = A+M+C
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ADC_ZPG: { exec_sum(); };
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ADC_ZPG: { exec_sum(); };
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ADC_ZPX: { exec_sum(); };
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ADC_ZPX: { exec_sum(); };
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ADC_ABS: { exec_sum(); };
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ADC_ABS: { exec_sum(); };
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ADC_ABX: { exec_sum(); };
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ADC_ABX: { exec_sum(); };
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ADC_ABY: { exec_sum(); };
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ADC_ABY: { exec_sum(); };
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ADC_IDX: { exec_sum(); };
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ADC_IDX: { exec_sum(); };
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ADC_IDY: { exec_sum(); };
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ADC_IDY: { exec_sum(); };
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AND_IMM: { exec_and(); }; // A,Z,N = A&M
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AND_IMM: { exec_and(); }; // A,Z,N = A&M
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AND_ZPG: { exec_and(); };
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AND_ZPG: { exec_and(); };
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AND_ZPX: { exec_and(); };
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AND_ZPX: { exec_and(); };
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AND_ABS: { exec_and(); };
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AND_ABS: { exec_and(); };
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AND_ABX: { exec_and(); };
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AND_ABX: { exec_and(); };
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AND_ABY: { exec_and(); };
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AND_ABY: { exec_and(); };
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AND_IDX: { exec_and(); };
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AND_IDX: { exec_and(); };
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AND_IDY: { exec_and(); };
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AND_IDY: { exec_and(); };
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ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
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ASL_ACC: { exec_asl_acc(); }; // A,Z,C,N = M*2
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ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPG: { exec_asl_mem(); }; // M,Z,C,N = M*2
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ZPX: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABS: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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ASL_ABX: { exec_asl_mem(); };
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BCC_REL: {}; // nothing is done. these are all branches.
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BCC_REL: {}; // nothing is done. these are all branches.
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BCS_REL: {};
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BCS_REL: {};
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BEQ_REL: {};
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BEQ_REL: {};
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BMI_REL: {};
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BMI_REL: {};
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BNE_REL: {};
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BNE_REL: {};
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BPL_REL: {};
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BPL_REL: {};
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BVC_REL: {};
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BVC_REL: {};
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BVS_REL: {};
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BVS_REL: {};
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BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
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BIT_ZPG: { exec_bit(); }; // Z = A & M, N = M7, V = M6
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BIT_ABS: { exec_bit(); };
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BIT_ABS: { exec_bit(); };
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BRK_IMP: { reg_status[4:4] = 1; };
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BRK_IMP: { reg_status[4:4] = 1; };
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CLC_IMP: { reg_status[0:0] = 0; };
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CLC_IMP: { reg_status[0:0] = 0; };
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CLD_IMP: { reg_status[3:3] = 0; };
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CLD_IMP: { reg_status[3:3] = 0; };
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CLI_IMP: { reg_status[2:2] = 0; };
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CLI_IMP: { reg_status[2:2] = 0; };
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CLV_IMP: { reg_status[6:6] = 0; };
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CLV_IMP: { reg_status[6:6] = 0; };
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CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
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CMP_IMM: { exec_cmp(reg_a); }; // Z,C,N = A-M
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CMP_ZPG: { exec_cmp(reg_a); };
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CMP_ZPG: { exec_cmp(reg_a); };
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CMP_ZPX: { exec_cmp(reg_a); };
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CMP_ZPX: { exec_cmp(reg_a); };
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CMP_ABS: { exec_cmp(reg_a); };
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CMP_ABS: { exec_cmp(reg_a); };
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CMP_ABX: { exec_cmp(reg_a); };
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CMP_ABX: { exec_cmp(reg_a); };
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CMP_ABY: { exec_cmp(reg_a); };
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CMP_ABY: { exec_cmp(reg_a); };
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CMP_IDX: { exec_cmp(reg_a); };
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CMP_IDX: { exec_cmp(reg_a); };
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CMP_IDY: { exec_cmp(reg_a); };
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CMP_IDY: { exec_cmp(reg_a); };
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CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
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CPX_IMM: { exec_cmp(reg_x); }; // Z,C,N = X-M
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CPX_ZPG: { exec_cmp(reg_x); };
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CPX_ZPG: { exec_cmp(reg_x); };
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CPX_ABS: { exec_cmp(reg_x); };
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CPX_ABS: { exec_cmp(reg_x); };
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CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
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CPY_IMM: { exec_cmp(reg_y); }; //Z,C,N = Y-M
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CPY_ZPG: { exec_cmp(reg_y); };
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CPY_ZPG: { exec_cmp(reg_y); };
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CPY_ABS: { exec_cmp(reg_y); };
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CPY_ABS: { exec_cmp(reg_y); };
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DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
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DEC_ZPG: { exec_dec(inst.alu_a, TRUE); }; // M,Z,N = M-1
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DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
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DEC_ZPX: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABS: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
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DEC_ABX: { exec_dec(inst.alu_a, TRUE); };
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DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1
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DEX_IMP: { exec_dec(reg_x, FALSE); }; // X,Z,N = X-1
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DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1
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DEY_IMP: { exec_dec(reg_y, FALSE); }; // Y,Z,N = Y-1
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EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
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EOR_IMM: { exec_eor(); }; // A,Z,N = A^M
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EOR_ZPG: { exec_eor(); };
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EOR_ZPG: { exec_eor(); };
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EOR_ZPX: { exec_eor(); };
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EOR_ZPX: { exec_eor(); };
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EOR_ABS: { exec_eor(); };
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EOR_ABS: { exec_eor(); };
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EOR_ABX: { exec_eor(); };
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EOR_ABX: { exec_eor(); };
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EOR_ABY: { exec_eor(); };
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EOR_ABY: { exec_eor(); };
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EOR_IDX: { exec_eor(); };
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EOR_IDX: { exec_eor(); };
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EOR_IDY: { exec_eor(); };
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EOR_IDY: { exec_eor(); };
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INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
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INC_ZPG: { exec_inc(inst.alu_a, TRUE); };
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INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
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INC_ZPX: { exec_inc(inst.alu_a, TRUE); };
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INC_ABS: { exec_inc(inst.alu_a, TRUE); };
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INC_ABS: { exec_inc(inst.alu_a, TRUE); };
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INC_ABX: { exec_inc(inst.alu_a, TRUE); };
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INC_ABX: { exec_inc(inst.alu_a, TRUE); };
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INX_IMP: { exec_inc(reg_x, FALSE); };
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INX_IMP: { exec_inc(reg_x, FALSE); };
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INY_IMP: { exec_inc(reg_y, FALSE); };
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INY_IMP: { exec_inc(reg_y, FALSE); };
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JMP_ABS: {};
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JMP_ABS: {};
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JMP_IND: {};
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JMP_IND: {};
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JSR_ABS: {};
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JSR_ABS: {};
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LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
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LDA_IMM: { exec_load(reg_a, TRUE); }; // A,Z,N = M
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LDA_ZPG: { exec_load(reg_a, TRUE); };
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LDA_ZPG: { exec_load(reg_a, TRUE); };
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LDA_ZPX: { exec_load(reg_a, TRUE); };
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LDA_ZPX: { exec_load(reg_a, TRUE); };
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LDA_ABS: { exec_load(reg_a, TRUE); };
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LDA_ABS: { exec_load(reg_a, TRUE); };
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LDA_ABX: { exec_load(reg_a, TRUE); };
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LDA_ABX: { exec_load(reg_a, TRUE); };
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LDA_ABY: { exec_load(reg_a, TRUE); };
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LDA_ABY: { exec_load(reg_a, TRUE); };
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LDA_IDX: { exec_load(reg_a, TRUE); };
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LDA_IDX: { exec_load(reg_a, TRUE); };
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LDA_IDY: { exec_load(reg_a, TRUE); };
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LDA_IDY: { exec_load(reg_a, TRUE); };
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LDX_IMM: { exec_load(reg_x, FALSE); };
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LDX_IMM: { exec_load(reg_x, FALSE); };
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LDX_ZPG: { exec_load(reg_x, FALSE); };
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LDX_ZPG: { exec_load(reg_x, FALSE); };
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LDX_ZPY: { exec_load(reg_x, FALSE); };
|
LDX_ZPY: { exec_load(reg_x, FALSE); };
|
LDX_ABS: { exec_load(reg_x, FALSE); };
|
LDX_ABS: { exec_load(reg_x, FALSE); };
|
LDX_ABY: { exec_load(reg_x, FALSE); };
|
LDX_ABY: { exec_load(reg_x, FALSE); };
|
|
|
LDY_IMM: { exec_load(reg_y, FALSE); };
|
LDY_IMM: { exec_load(reg_y, FALSE); };
|
LDY_ZPG: { exec_load(reg_y, FALSE); };
|
LDY_ZPG: { exec_load(reg_y, FALSE); };
|
LDY_ZPX: { exec_load(reg_y, FALSE); };
|
LDY_ZPX: { exec_load(reg_y, FALSE); };
|
LDY_ABS: { exec_load(reg_y, FALSE); };
|
LDY_ABS: { exec_load(reg_y, FALSE); };
|
LDY_ABX: { exec_load(reg_y, FALSE); };
|
LDY_ABX: { exec_load(reg_y, FALSE); };
|
|
|
LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
|
LSR_ACC: { exec_lsr(reg_a); }; // A,C,Z,N = A/2 or M,C,Z,N = M/2
|
LSR_ZPG: { exec_lsr(inst.alu_a); };
|
LSR_ZPG: { exec_lsr(inst.alu_a); };
|
LSR_ZPX: { exec_lsr(inst.alu_a); };
|
LSR_ZPX: { exec_lsr(inst.alu_a); };
|
LSR_ABS: { exec_lsr(inst.alu_a); };
|
LSR_ABS: { exec_lsr(inst.alu_a); };
|
LSR_ABX: { exec_lsr(inst.alu_a); };
|
LSR_ABX: { exec_lsr(inst.alu_a); };
|
|
|
NOP_IMP: {};
|
NOP_IMP: {};
|
|
|
ORA_IMM: { exec_or(); }; // A,Z,N = A|M
|
ORA_IMM: { exec_or(); }; // A,Z,N = A|M
|
ORA_ZPG: { exec_or(); };
|
ORA_ZPG: { exec_or(); };
|
ORA_ZPX: { exec_or(); };
|
ORA_ZPX: { exec_or(); };
|
ORA_ABS: { exec_or(); };
|
ORA_ABS: { exec_or(); };
|
ORA_ABX: { exec_or(); };
|
ORA_ABX: { exec_or(); };
|
ORA_ABY: { exec_or(); };
|
ORA_ABY: { exec_or(); };
|
ORA_IDX: { exec_or(); };
|
ORA_IDX: { exec_or(); };
|
ORA_IDY: { exec_or(); };
|
ORA_IDY: { exec_or(); };
|
|
|
PHA_IMP: { reg_result = reg_a; };
|
PHA_IMP: { reg_result = reg_a; };
|
PHP_IMP: {}; // P is always connected and the result is not updated
|
PHP_IMP: {}; // P is always connected and the result is not updated
|
PLA_IMP: {
|
PLA_IMP: {
|
reg_a = inst.alu_a;
|
reg_a = inst.alu_a;
|
reg_result = inst.alu_a;
|
reg_result = inst.alu_a;
|
update_z(reg_a);
|
update_z(reg_a);
|
update_n(reg_a);
|
update_n(reg_a);
|
};
|
};
|
PLP_IMP: {
|
PLP_IMP: {
|
reg_status = inst.alu_a;
|
reg_status = inst.alu_a;
|
reg_status[5:5] = 1; // this is always one
|
reg_status[5:5] = 1; // this is always one
|
};
|
};
|
|
|
ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
|
ROL_ACC: { exec_rot(TRUE, reg_a); reg_a = reg_result; };
|
ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPG: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ZPX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABS: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
|
ROL_ABX: { exec_rot(TRUE, inst.alu_a); };
|
ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
|
ROR_ACC: { exec_rot(FALSE, reg_a); reg_a = reg_result; };
|
ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPG: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ZPX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABS: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
|
ROR_ABX: { exec_rot(FALSE, inst.alu_a); };
|
|
|
RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
|
RTI_IMP: { reg_status = inst.alu_a; reg_status[5:5] = 1; };
|
RTS_IMP: { };
|
RTS_IMP: { };
|
|
|
SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
|
SBC_IMM: { exec_sub(); }; // A,Z,C,N = A-M-(1-C)
|
SBC_ZPG: { exec_sub(); };
|
SBC_ZPG: { exec_sub(); };
|
SBC_ZPX: { exec_sub(); };
|
SBC_ZPX: { exec_sub(); };
|
SBC_ABS: { exec_sub(); };
|
SBC_ABS: { exec_sub(); };
|
SBC_ABX: { exec_sub(); };
|
SBC_ABX: { exec_sub(); };
|
SBC_ABY: { exec_sub(); };
|
SBC_ABY: { exec_sub(); };
|
SBC_IDX: { exec_sub(); };
|
SBC_IDX: { exec_sub(); };
|
SBC_IDY: { exec_sub(); };
|
SBC_IDY: { exec_sub(); };
|
|
|
SEC_IMP: { reg_status[0:0] = 1; };
|
SEC_IMP: { reg_status[0:0] = 1; };
|
SED_IMP: { reg_status[3:3] = 1; };
|
SED_IMP: { reg_status[3:3] = 1; };
|
SEI_IMP: { reg_status[2:2] = 1; };
|
SEI_IMP: { reg_status[2:2] = 1; };
|
|
|
STA_ZPG: { reg_result = reg_a; };
|
STA_ZPG: { reg_result = reg_a; };
|
STA_ZPX: { reg_result = reg_a; };
|
STA_ZPX: { reg_result = reg_a; };
|
STA_ABS: { reg_result = reg_a; };
|
STA_ABS: { reg_result = reg_a; };
|
STA_ABX: { reg_result = reg_a; };
|
STA_ABX: { reg_result = reg_a; };
|
STA_ABY: { reg_result = reg_a; };
|
STA_ABY: { reg_result = reg_a; };
|
STA_IDX: { reg_result = reg_a; };
|
STA_IDX: { reg_result = reg_a; };
|
STA_IDY: { reg_result = reg_a; };
|
STA_IDY: { reg_result = reg_a; };
|
STX_ZPG: { };
|
STX_ZPG: { };
|
STX_ZPY: { };
|
STX_ZPY: { };
|
STX_ABS: { };
|
STX_ABS: { };
|
STY_ZPG: { };
|
STY_ZPG: { };
|
STY_ZPX: { };
|
STY_ZPX: { };
|
STY_ABS: { };
|
STY_ABS: { };
|
|
|
TAX_IMP: { exec_transfer(reg_a, reg_x); };
|
TAX_IMP: { exec_transfer(reg_a, reg_x); };
|
TAY_IMP: { exec_transfer(reg_a, reg_y); };
|
TAY_IMP: { exec_transfer(reg_a, reg_y); };
|
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
|
TSX_IMP: { exec_transfer(inst.alu_a, reg_x); };
|
TXA_IMP: { exec_transfer(reg_x, reg_a); };
|
TXA_IMP: { exec_transfer(reg_x, reg_a); };
|
TXS_IMP: { };
|
TXS_IMP: { };
|
TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
|
TYA_IMP: { exec_transfer(reg_y, reg_a); }; // A = Y
|
|
|
// note: tya and txa do not update the result register
|
// note: tya and txa do not update the result register
|
|
|
default: {
|
default: {
|
// all the random generated opcodes will fall here
|
// all the random generated opcodes will fall here
|
}
|
}
|
};
|
};
|
};
|
};
|
|
|
exec_transfer(source : byte, dest : *byte) is {
|
exec_transfer(source : byte, dest : *byte) is {
|
dest = source;
|
dest = source;
|
update_z(dest);
|
update_z(dest);
|
update_n(dest);
|
update_n(dest);
|
};
|
};
|
|
|
exec_sub() is {
|
exec_sub() is {
|
if (reg_status[3:3] == 1) { // decimal
|
if (reg_status[3:3] == 1) { // decimal
|
var op1 : int;
|
var op1 : int;
|
var op2 : int;
|
var op2 : int;
|
|
|
warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
|
warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
|
|
|
//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
//out("i am subtracting ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
|
|
op1 = inst.alu_a[3:0];
|
op1 = inst.alu_a[3:0];
|
op2 = inst.alu_a[7:4];
|
op2 = inst.alu_a[7:4];
|
|
|
op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
|
op1 = reg_a[3:0] - op1 -1 + reg_status[0:0];
|
op2 = reg_a[7:4] - op2;
|
op2 = reg_a[7:4] - op2;
|
|
|
if (op1 >= 10) {
|
if (op1 >= 10) {
|
op2 = op2 + op1/10;
|
op2 = op2 + op1/10;
|
op1 = op1 % 10;
|
op1 = op1 % 10;
|
} else if (op1 < 0) {
|
} else if (op1 < 0) {
|
op2 = op2 - op1/10;
|
op2 = op2 - op1/10;
|
op1 = -(op1 % 10);
|
op1 = -(op1 % 10);
|
};
|
};
|
|
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
|
|
if (op2 >= 10) {
|
if (op2 >= 10) {
|
op2 = op2 % 10;
|
op2 = op2 % 10;
|
}
|
}
|
else if (op2 < 0) {
|
else if (op2 < 0) {
|
op2 = op2 + 10;
|
op2 = op2 + 10;
|
reg_status[0:0] = 0;
|
reg_status[0:0] = 0;
|
};
|
};
|
|
|
reg_result[3:0] = op1;
|
reg_result[3:0] = op1;
|
reg_result[7:4] = op2;
|
reg_result[7:4] = op2;
|
|
|
update_n(reg_result);
|
update_n(reg_result);
|
update_z(reg_result);
|
update_z(reg_result);
|
update_v(reg_a, inst.alu_a, reg_result);
|
update_v(reg_a, inst.alu_a, reg_result);
|
reg_a = reg_result;
|
reg_a = reg_result;
|
}
|
}
|
else {
|
else {
|
var temp: int;
|
var temp: int;
|
|
|
temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
|
temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
|
reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
|
reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
|
|
|
reg_status[7:7] = temp[7:7]; // N
|
reg_status[7:7] = temp[7:7]; // N
|
print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
|
//print (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
|
reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
|
reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
|
|
|
if (reg_result == 0) {
|
if (reg_result == 0) {
|
reg_status[1:1] = 1; // Z
|
reg_status[1:1] = 1; // Z
|
} else {
|
} else {
|
reg_status[1:1] = 0; // Z
|
reg_status[1:1] = 0; // Z
|
};
|
};
|
|
|
reg_a = temp.as_a(byte);
|
reg_a = temp.as_a(byte);
|
|
|
print (temp & 0xff00);
|
//print (temp & 0xff00);
|
print (temp & 0xff00) != 0x0000;
|
//print (temp & 0xff00) != 0x0000;
|
|
|
if ( (temp & 0xff00) != 0x0000 ) {
|
if ( (temp & 0xff00) != 0x0000 ) {
|
reg_status[0:0] = 0;
|
reg_status[0:0] = 0;
|
} else {
|
} else {
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
}
|
}
|
|
|
};
|
};
|
};
|
};
|
|
|
exec_rot(left : bool, arg1 : byte) is {
|
exec_rot(left : bool, arg1 : byte) is {
|
var oldcarry : bit;
|
var oldcarry : bit;
|
|
|
if (left) {
|
if (left) {
|
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[7:7];
|
reg_status[0:0] = arg1[7:7];
|
reg_result = arg1 << 1;
|
reg_result = arg1 << 1;
|
reg_result[0:0] = oldcarry;
|
reg_result[0:0] = oldcarry;
|
}
|
}
|
else {
|
else {
|
oldcarry = reg_status[0:0];
|
oldcarry = reg_status[0:0];
|
reg_status[0:0] = arg1[0:0];
|
reg_status[0:0] = arg1[0:0];
|
reg_result = arg1 >> 1;
|
reg_result = arg1 >> 1;
|
reg_result[7:7] = oldcarry;
|
reg_result[7:7] = oldcarry;
|
};
|
};
|
|
|
update_z(reg_result);
|
update_z(reg_result);
|
update_n(reg_result);
|
update_n(reg_result);
|
};
|
};
|
|
|
exec_or() is {
|
exec_or() is {
|
reg_a = reg_a | inst.alu_a;
|
reg_a = reg_a | inst.alu_a;
|
reg_result = reg_a;
|
reg_result = reg_a;
|
update_z(reg_a);
|
update_z(reg_a);
|
update_n(reg_a);
|
update_n(reg_a);
|
};
|
};
|
|
|
exec_lsr(arg1 : *byte) is {
|
exec_lsr(arg1 : *byte) is {
|
reg_status[0:0] = arg1[0:0];
|
reg_status[0:0] = arg1[0:0];
|
arg1 = arg1 >> 1;
|
arg1 = arg1 >> 1;
|
update_z(arg1);
|
update_z(arg1);
|
update_n(arg1);
|
update_n(arg1);
|
reg_result = arg1;
|
reg_result = arg1;
|
};
|
};
|
|
|
exec_load(arg1 : *byte, update_result : bool) is {
|
exec_load(arg1 : *byte, update_result : bool) is {
|
arg1 = inst.alu_a;
|
arg1 = inst.alu_a;
|
|
|
if (update_result) { //
|
if (update_result) { //
|
reg_result = inst.alu_a; // no need for this but...
|
reg_result = inst.alu_a; // no need for this but...
|
};
|
};
|
update_z(arg1);
|
update_z(arg1);
|
update_n(arg1);
|
update_n(arg1);
|
};
|
};
|
|
|
exec_inc(arg1 : *byte, update_result : bool) is {
|
exec_inc(arg1 : *byte, update_result : bool) is {
|
arg1 = arg1 + 1;
|
arg1 = arg1 + 1;
|
update_z(arg1);
|
update_z(arg1);
|
update_n(arg1);
|
update_n(arg1);
|
|
|
if (update_result) { //
|
if (update_result) { //
|
reg_result = arg1;
|
reg_result = arg1;
|
};
|
};
|
};
|
};
|
|
|
exec_eor() is {
|
exec_eor() is {
|
reg_a = reg_a ^ inst.alu_a;
|
reg_a = reg_a ^ inst.alu_a;
|
reg_result = reg_a;
|
reg_result = reg_a;
|
update_z(reg_a);
|
update_z(reg_a);
|
update_n(reg_a);
|
update_n(reg_a);
|
};
|
};
|
|
|
exec_dec(arg1 : *byte, update_result : bool) is {
|
exec_dec(arg1 : *byte, update_result : bool) is {
|
arg1 = arg1 - 1;
|
arg1 = arg1 - 1;
|
update_z(arg1);
|
update_z(arg1);
|
update_n(arg1);
|
update_n(arg1);
|
|
|
if (update_result) { // DEX and DEY do not output the result
|
if (update_result) { // DEX and DEY do not output the result
|
reg_result = arg1;
|
reg_result = arg1;
|
};
|
};
|
};
|
};
|
|
|
exec_cmp(arg1 : byte) is {
|
exec_cmp(arg1 : byte) is {
|
update_z(arg1 - inst.alu_a);
|
update_z(arg1 - inst.alu_a);
|
update_n(arg1 - inst.alu_a);
|
update_n(arg1 - inst.alu_a);
|
|
|
if (arg1 >= inst.alu_a) {
|
if (arg1 >= inst.alu_a) {
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
}
|
}
|
else {
|
else {
|
reg_status[0:0] = 0;
|
reg_status[0:0] = 0;
|
};
|
};
|
};
|
};
|
|
|
exec_bit() is {
|
exec_bit() is {
|
update_z(reg_a & inst.alu_a);
|
update_z(reg_a & inst.alu_a);
|
reg_status[7:7] = inst.alu_a[7:7];
|
reg_status[7:7] = inst.alu_a[7:7];
|
reg_status[6:6] = inst.alu_a[6:6];
|
reg_status[6:6] = inst.alu_a[6:6];
|
};
|
};
|
|
|
exec_asl_acc() is {
|
exec_asl_acc() is {
|
reg_status[0:0] = reg_a[7:7];
|
reg_status[0:0] = reg_a[7:7];
|
reg_a = reg_a * 2;
|
reg_a = reg_a * 2;
|
update_z(reg_a);
|
update_z(reg_a);
|
update_n(reg_a);
|
update_n(reg_a);
|
reg_result = reg_a;
|
reg_result = reg_a;
|
};
|
};
|
|
|
exec_asl_mem() is {
|
exec_asl_mem() is {
|
reg_status[0:0] = inst.alu_a[7:7];
|
reg_status[0:0] = inst.alu_a[7:7];
|
reg_result = inst.alu_a * 2;
|
reg_result = inst.alu_a * 2;
|
update_z(reg_result);
|
update_z(reg_result);
|
update_n(reg_result);
|
update_n(reg_result);
|
};
|
};
|
|
|
exec_and() is {
|
exec_and() is {
|
reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
|
reg_a = reg_a & inst.alu_a; // TODO: this is probably wrong
|
update_z(reg_a);
|
update_z(reg_a);
|
update_n(reg_a);
|
update_n(reg_a);
|
reg_result = reg_a;
|
reg_result = reg_a;
|
};
|
};
|
|
|
exec_sum() is {
|
exec_sum() is {
|
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
//out("adding: ", reg_a, " + ", inst.alu_a, " + ", reg_status[0:0]);
|
if (reg_status[3:3] == 1) {
|
if (reg_status[3:3] == 1) {
|
var op1 : byte;
|
var op1 : byte;
|
var op2 : byte;
|
var op2 : byte;
|
|
var aux : byte;
|
|
|
//out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
|
//out("i am adding ", reg_a, " and ", inst.alu_a, " carry is ", reg_status[0:0]);
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op1 = inst.alu_a[3:0];
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op1 = reg_a[3:0] + inst.alu_a[3:0] + reg_status[0:0];
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op2 = inst.alu_a[7:4];
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print op1;
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//Int32 lo = (A & 0x0f) + (operand & 0x0f) + (C ? 1 : 0);
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op2 = reg_a[7:4] + inst.alu_a[7:4];
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//carry_aux = reg_a[7:4] + inst.alu_a[7:4];
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print op2;
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//Int32 hi = (A & 0xf0) + (operand & 0xf0);
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|
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op1 = reg_a[3:0] + op1 + reg_status[0:0];
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aux = op1 + op2;
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op2 = reg_a[7:4] + op2;
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|
|
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if (op1 >= 10) {
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if (aux[7:0] == 0) {
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op2 = op2 + op1/ 10;
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reg_status[1:1] = 1;
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op1 = op1 % 10;
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};
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|
|
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if (op2 >= 10) {
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op2 = op2 % 10;
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reg_status[0:0] = 1;
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}
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}
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else {
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else {
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reg_status[0:0] = 0;
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reg_status[1:1] = 0;
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};
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};
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//notZ = (lo+hi) & 0xff;
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|
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reg_result[3:0] = op1;
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if (op1 > 0x09) {
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reg_result[7:4] = op2;
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op2 += 0x01;
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update_z(reg_result);
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op1 += 0x06;
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update_n(reg_result);
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};
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update_v(reg_a, inst.alu_a, reg_result);
|
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reg_a = reg_result;
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reg_status[7:7] = op2[3:3];
|
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//N = hi & 0x80;
|
|
|
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reg_status[6:6] = ~(reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ op2[3:3]); // V
|
|
//V = ~(A ^ operand) & (A ^ hi) & 0x80;
|
|
print op2;
|
|
if (op2 > 0x09) {
|
|
op2 += 0x06;
|
|
print op2;
|
|
};
|
|
//if (hi > 0x90) hi += 0x60;
|
|
|
|
reg_status[0:0] = (op2 > 15) ? 1 : 0;
|
|
//C = hi & 0xff00;
|
|
|
|
reg_a[3:0] = op1[3:0];
|
|
reg_a[7:4] = op2[3:0];
|
|
//reg_a = (lo & 0x0f) + (hi & 0xf0);
|
|
|
|
reg_result = reg_a;
|
}
|
}
|
else { // stella checked
|
else { // stella checked
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
reg_result = reg_a + inst.alu_a + reg_status[0:0];
|
update_n(reg_result);
|
update_n(reg_result);
|
update_v(reg_a, inst.alu_a, reg_result);
|
update_v(reg_a, inst.alu_a, reg_result);
|
update_z(reg_result);
|
update_z(reg_result);
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
update_c(reg_a, inst.alu_a, reg_status[0:0]);
|
|
|
reg_a = reg_result;
|
reg_a = reg_result;
|
};
|
};
|
};
|
};
|
|
|
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
|
update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
|
if (arg1 + arg2 + arg3 > 255) {
|
if (arg1 + arg2 + arg3 > 255) {
|
reg_status[0:0] = 1;
|
reg_status[0:0] = 1;
|
}
|
}
|
else {
|
else {
|
reg_status[0:0] = 0;
|
reg_status[0:0] = 0;
|
}
|
}
|
};
|
};
|
|
|
update_v(op1 : byte, op2 : byte, res : byte) is {
|
update_v(op1 : byte, op2 : byte, res : byte) is {
|
if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
|
if ((op1[7:7] == op2[7:7]) && (op1[7:7] != res[7:7])) {
|
reg_status[6:6] = 1;
|
reg_status[6:6] = 1;
|
}
|
}
|
else {
|
else {
|
reg_status[6:6] = 0;
|
reg_status[6:6] = 0;
|
};
|
};
|
};
|
};
|
|
|
update_z(arg : byte) is {
|
update_z(arg : byte) is {
|
if (arg == 0) {
|
if (arg == 0) {
|
reg_status[1:1] = 1;
|
reg_status[1:1] = 1;
|
}
|
}
|
else {
|
else {
|
reg_status[1:1] = 0;
|
reg_status[1:1] = 0;
|
}
|
}
|
};
|
};
|
|
|
|
|
update_n(arg : byte) is {
|
update_n(arg : byte) is {
|
if (arg[7:7] == 1) {
|
if (arg[7:7] == 1) {
|
reg_status[7:7] = 1;
|
reg_status[7:7] = 1;
|
}
|
}
|
else {
|
else {
|
reg_status[7:7] = 0;
|
reg_status[7:7] = 0;
|
}
|
}
|
};
|
};
|
};
|
};
|
'>
|
'>
|
|
|
