////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// t2600 IP Core ////
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//// t2600 IP Core ////
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//// ////
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//// ////
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//// This file is part of the t2600 project ////
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//// This file is part of the t2600 project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// VGA controller ////
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//// VGA controller ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Feed the controller with data ////
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//// - Feed the controller with data ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter);
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module controller_test(reset_n, clk_50, pixel, vert_counter, hor_counter);
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input reset_n;
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input reset_n;
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input clk_50;
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input clk_50;
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output reg [11:0] pixel;
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output reg [11:0] pixel;
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output reg [8:0] vert_counter;
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output reg [8:0] vert_counter;
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output reg [7:0] hor_counter;
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output reg [7:0] hor_counter;
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reg clk_358; // 3.58mhz
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reg clk_358; // 3.58mhz
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reg [3:0] counter;
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reg [3:0] counter;
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reg [3:0] red;
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reg [3:0] red;
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reg [3:0] green;
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reg [3:0] green;
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reg [3:0] blue;
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reg [3:0] blue;
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always @ (posedge clk_50 or negedge reset_n) begin
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always @ (posedge clk_50 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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clk_358 <= 1'b0;
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clk_358 <= 1'b0;
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counter <= 4'd0;
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counter <= 4'd0;
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red <= 4'b1010;
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red <= 4'b1010;
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green <= 4'b0001;
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green <= 4'b0001;
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blue <= 4'b1110;
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blue <= 4'b1110;
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end
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end
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else begin
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else begin
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red <= 4'b1010;
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red <= 4'b1010;
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green <= 4'b0001;
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green <= 4'b0001;
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blue <= 4'b1110;
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blue <= 4'b1110;
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if (counter == 4'h6) begin
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if (counter == 4'h6) begin
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clk_358 <= !clk_358;
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clk_358 <= !clk_358;
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counter <= 4'd0;
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counter <= 4'd0;
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end
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end
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else begin
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else begin
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counter <= counter + 4'd1;
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counter <= counter + 4'd1;
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end
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end
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end
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end
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end
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end
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always @ (posedge clk_358 or negedge reset_n) begin
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always @ (posedge clk_358 or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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vert_counter <= 6'd0;
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hor_counter <= 8'd0;
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hor_counter <= 8'd0;
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vert_counter = 9'd0;
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vert_counter <= 9'd0;
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end
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end
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else begin
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else begin
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if (hor_counter == 8'd227) begin // last colum
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if (hor_counter == 8'd227) begin // last colum
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hor_counter <= 8'd0;
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hor_counter <= 8'd0;
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if (vert_counter == 9'd261) begin // last line
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if (vert_counter == 9'd261) begin // last line
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vert_counter <= 9'd0;
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vert_counter <= 9'd0;
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end
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end
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else begin
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else begin
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vert_counter <= vert_counter + 9'd1;
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vert_counter <= vert_counter + 9'd1;
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end
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end
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end
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end
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else begin
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else begin
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hor_counter <= hor_counter + 8'd1;
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hor_counter <= hor_counter + 8'd1;
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end
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end
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end
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end
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end
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end
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always @(*) begin // comb logic
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always @(*) begin // comb logic
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pixel = {red, green, blue};
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pixel = {red, green, blue};
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end
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end
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endmodule
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endmodule
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