////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// t2600 IP Core ////
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//// t2600 IP Core ////
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//// ////
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//// ////
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//// This file is part of the t2600 project ////
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//// This file is part of the t2600 project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Bus controller for linking the t6507, t6532 and txxx. TODO ////
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//// Bus controller for linking the t6507, t6532 and txxx. TODO ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Everything ////
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//// - Nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t2600_bus(address, data_from_cpu, cpu_rw_mem, riot_data, rom_data, tia_data, address_riot, address_rom, address_tia, data_to_cpu, enable_riot, enable_rom, enable_tia, rw_mem);
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module t2600_bus(address, data_from_cpu, cpu_rw_mem, riot_data, rom_data, tia_data, address_riot, address_rom, address_tia, data_to_cpu, enable_riot, enable_rom, enable_tia, rw_mem);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd13;
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parameter [3:0] ADDR_SIZE = 4'd13;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] RIOT_ADDR_SIZE_ = 4'd6;
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localparam [3:0] RIOT_ADDR_SIZE_ = 4'd6;
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localparam [3:0] TIA_ADDR_SIZE_ = 4'd5;
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localparam [3:0] TIA_ADDR_SIZE_ = 4'd5;
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input [ADDR_SIZE_:0] address;
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input [ADDR_SIZE_:0] address;
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input [DATA_SIZE_:0] data_from_cpu;
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input [DATA_SIZE_:0] data_from_cpu;
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input cpu_rw_mem;
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input cpu_rw_mem;
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inout [DATA_SIZE_:0] riot_data;
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inout [DATA_SIZE_:0] riot_data;
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inout [DATA_SIZE_:0] rom_data;
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inout [DATA_SIZE_:0] rom_data;
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inout [DATA_SIZE_:0] tia_data;
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inout [DATA_SIZE_:0] tia_data;
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output reg [RIOT_ADDR_SIZE_:0] address_riot;
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output reg [RIOT_ADDR_SIZE_:0] address_riot;
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output reg [ADDR_SIZE_:0] address_rom;
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output reg [ADDR_SIZE_:0] address_rom;
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output reg [TIA_ADDR_SIZE_:0] address_tia;
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output reg [TIA_ADDR_SIZE_:0] address_tia;
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output reg[DATA_SIZE_:0] data_to_cpu;
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output reg[DATA_SIZE_:0] data_to_cpu;
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output reg enable_riot;
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output reg enable_riot;
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output reg enable_rom;
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output reg enable_rom;
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output reg enable_tia;
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output reg enable_tia;
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output reg rw_mem;
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output reg rw_mem;
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assign riot_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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assign riot_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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assign rom_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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assign rom_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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assign tia_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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assign tia_data = (rw_mem) ? data_from_cpu : 8'bZ; // if i am writing the bus receives the data from cpu
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always @(*) begin
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always @(*) begin
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enable_riot = 1'b0;
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enable_riot = 1'b0;
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enable_rom = 1'b0;
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enable_rom = 1'b0;
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enable_tia = 1'b0;
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enable_tia = 1'b0;
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rw_mem = cpu_rw_mem;
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rw_mem = cpu_rw_mem;
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address_tia = address[5:0];
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address_tia = address[5:0];
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address_riot = address[6:0];
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address_riot = address[6:0];
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address_rom = address;
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address_rom = address;
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if (address[12]) begin
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if (address[12]) begin
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data_to_cpu = rom_data;
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data_to_cpu = rom_data;
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enable_rom = 1'b1;
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enable_rom = 1'b1;
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end
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end
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else if (address[7]) begin
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else if (address[7]) begin
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data_to_cpu = riot_data;
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data_to_cpu = riot_data;
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enable_riot = 1'b1;
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enable_riot = 1'b1;
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end
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end
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else begin
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else begin
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data_to_cpu = tia_data;
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data_to_cpu = tia_data;
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enable_tia = 1'b1;
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enable_tia = 1'b1;
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end
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end
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end
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end
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endmodule
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endmodule
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