////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// T6507LP IP Core ////
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//// T6507LP IP Core ////
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//// ////
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//// ////
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//// This file is part of the T6507LP project ////
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//// This file is part of the T6507LP project ////
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//// http://www.opencores.org/cores/t6507lp/ ////
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//// http://www.opencores.org/cores/t6507lp/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6507 ALU ////
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//// 6507 ALU ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// - Search for TODO ////
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//// - Search for TODO ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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// TODO: verify code identation
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// TODO: verify code identation
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module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
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module t6507lp_alu( clk, reset_n, alu_enable, alu_result, alu_status, alu_opcode, alu_a, alu_x, alu_y );
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input wire clk;
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input wire clk;
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input wire reset_n;
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input wire reset_n;
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input wire alu_enable;
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input wire alu_enable;
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input wire [7:0] alu_opcode;
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input wire [7:0] alu_opcode;
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input wire [7:0] alu_a;
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input wire [7:0] alu_a;
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output reg [7:0] alu_result;
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output reg [7:0] alu_result;
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output reg [7:0] alu_status;
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output reg [7:0] alu_status;
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output reg [7:0] alu_x;
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output reg [7:0] alu_x;
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output reg [7:0] alu_y;
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output reg [7:0] alu_y;
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reg [7:0] A;
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reg [7:0] A;
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//reg [7:0] X;
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//reg [7:0] X;
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//reg [7:0] Y;
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//reg [7:0] Y;
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reg [7:0] STATUS;
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reg [7:0] STATUS;
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reg [7:0] result;
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reg [7:0] result;
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reg [7:0] op1;
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reg [7:0] op1;
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reg [7:0] op2;
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reg [7:0] op2;
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reg [7:0] bcdl;
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reg [7:0] bcdl;
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reg [7:0] bcdh;
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reg [7:0] bcdh;
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reg [7:0] bcdh2;
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reg [7:0] bcdh2;
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reg [7:0] AL;
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reg [7:0] AL;
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reg [7:0] AH;
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reg [7:0] AH;
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//reg C_aux;
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reg C_aux;
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reg sign;
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reg sign;
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`include "t6507lp_package.v"
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`include "t6507lp_package.v"
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always @ (posedge clk or negedge reset_n)
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always @ (posedge clk or negedge reset_n)
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begin
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begin
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if (reset_n == 0) begin
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if (reset_n == 0) begin
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alu_result <= 0;
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alu_result <= 0;
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alu_status[C] <= 0;
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alu_status[C] <= 0;
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alu_status[N] <= 0;
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alu_status[N] <= 0;
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alu_status[V] <= 0;
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alu_status[V] <= 0;
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alu_status[5] <= 1;
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alu_status[5] <= 1;
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alu_status[Z] <= 1;
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alu_status[Z] <= 1;
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alu_status[I] <= 0;
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alu_status[I] <= 0;
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alu_status[B] <= 0;
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alu_status[B] <= 0;
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alu_status[D] <= 0;
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alu_status[D] <= 0;
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A <= 0;
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A <= 0;
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//X <= 0;
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//Y <= 0;
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alu_x <= 0;
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alu_x <= 0;
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alu_y <= 0;
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alu_y <= 0;
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end
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end
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else if ( alu_enable == 1 ) begin
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else if ( alu_enable == 1 ) begin
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case (alu_opcode)
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case (alu_opcode)
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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ASL_ACC, EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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EOR_IDY, LSR_ACC, ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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ORA_IDX, ORA_IDY, ROL_ACC, ROR_ACC, SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY, LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS,
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP :
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LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY, PLA_IMP :
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begin
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begin
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A <= result;
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A <= result;
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY, TAX_IMP, TSX_IMP, INX_IMP, DEX_IMP :
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begin
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begin
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//X <= result;
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alu_x <= result;
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alu_x <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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TXS_IMP :
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TXS_IMP :
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begin
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begin
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//X <= result;
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alu_x <= result;
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alu_x <= result;
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end
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end
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TXA_IMP, TYA_IMP :
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TXA_IMP, TYA_IMP :
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begin
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begin
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A <= result;
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A <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
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LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX, TAY_IMP, INY_IMP, DEY_IMP :
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begin
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begin
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//Y <= result;
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alu_y <= result;
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alu_y <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
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CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY,
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CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
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CPX_IMM, CPX_ZPG, CPX_ABS, CPY_IMM, CPY_ZPG, CPY_ABS :
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begin
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begin
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
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PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
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alu_result <= result;
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alu_result <= result;
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end
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end
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STX_ZPG, STX_ZPY, STX_ABS : begin
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STX_ZPG, STX_ZPY, STX_ABS : begin
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alu_x <= result;
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alu_x <= result;
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end
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end
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STY_ZPG, STY_ZPX, STY_ABS : begin
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STY_ZPG, STY_ZPX, STY_ABS : begin
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alu_y <= result;
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alu_y <= result;
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end
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end
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SEC_IMP :
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SEC_IMP :
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begin
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begin
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alu_status[C] <= 1;
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alu_status[C] <= 1;
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end
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end
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SED_IMP :
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SED_IMP :
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begin
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begin
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alu_status[D] <= 1;
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alu_status[D] <= 1;
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end
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end
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SEI_IMP :
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SEI_IMP :
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begin
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begin
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alu_status[I] <= 1;
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alu_status[I] <= 1;
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end
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end
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CLC_IMP :
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CLC_IMP :
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begin
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begin
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alu_status[C] <= 0;
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alu_status[C] <= 0;
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end
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end
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CLD_IMP :
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CLD_IMP :
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begin
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begin
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alu_status[D] <= 0;
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alu_status[D] <= 0;
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end
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end
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CLI_IMP :
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CLI_IMP :
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begin
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begin
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alu_status[I] <= 0;
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alu_status[I] <= 0;
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end
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end
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CLV_IMP :
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CLV_IMP :
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begin
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begin
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alu_status[V] <= 0;
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alu_status[V] <= 0;
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end
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end
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BRK_IMP :
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BRK_IMP :
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begin
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begin
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alu_status[B] <= 1;
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alu_status[B] <= 1;
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end
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end
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PLP_IMP, RTI_IMP :
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PLP_IMP, RTI_IMP :
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begin
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begin
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alu_status[C] <= alu_a[C];
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alu_status[C] <= alu_a[C];
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alu_status[Z] <= alu_a[Z];
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alu_status[Z] <= alu_a[Z];
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alu_status[I] <= alu_a[I];
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alu_status[I] <= alu_a[I];
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alu_status[D] <= alu_a[D];
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alu_status[D] <= alu_a[D];
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alu_status[B] <= alu_a[B];
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alu_status[B] <= alu_a[B];
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alu_status[V] <= alu_a[V];
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alu_status[V] <= alu_a[V];
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alu_status[N] <= alu_a[N];
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alu_status[N] <= alu_a[N];
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alu_status[5] <= 1;
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alu_status[5] <= 1;
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end
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end
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BIT_ZPG, BIT_ABS :
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BIT_ZPG, BIT_ABS :
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begin
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begin
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alu_status[Z] <= STATUS[Z];
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alu_status[Z] <= STATUS[Z];
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alu_status[V] <= alu_a[6];
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alu_status[V] <= alu_a[6];
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alu_status[N] <= alu_a[7];
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alu_status[N] <= alu_a[7];
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end
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end
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
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INC_ZPG, INC_ZPX, INC_ABS, INC_ABX, DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX,
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ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
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ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX, LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX,
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
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ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX, ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX :
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begin
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begin
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alu_result <= result;
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alu_result <= result;
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alu_status <= STATUS;
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alu_status <= STATUS;
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end
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end
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//PHP_IMP : begin
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//end
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default : begin
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default : begin
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//$display("ERROR");
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|
end
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end
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endcase
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endcase
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end
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end
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end
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end
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always @ (*) begin
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always @ (*) begin
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if (alu_enable == 1) begin
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if (alu_enable == 1) begin
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//op1 = A;
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op1 = A;
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op1 = A;
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op2 = alu_a;
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op2 = alu_a;
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result = alu_result;
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result = alu_result;
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STATUS[N] = alu_status[N];
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STATUS[N] = alu_status[N];
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STATUS[C] = alu_status[C];
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STATUS[C] = alu_status[C];
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STATUS[V] = alu_status[V];
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STATUS[V] = alu_status[V];
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STATUS[B] = alu_status[B];
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STATUS[B] = alu_status[B];
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STATUS[I] = alu_status[I];
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STATUS[I] = alu_status[I];
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STATUS[D] = alu_status[D];
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STATUS[D] = alu_status[D];
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STATUS[Z] = alu_status[Z];
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STATUS[Z] = alu_status[Z];
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STATUS[5] = 1;
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STATUS[5] = 1;
|
|
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bcdl = 0;
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bcdl = 0;
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bcdh = 0;
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bcdh = 0;
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bcdh2 = 0;
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bcdh2 = 0;
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AL = 0;
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AL = 0;
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AH = 0;
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AH = 0;
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sign = op2[7];
|
sign = op2[7];
|
|
|
case (alu_opcode)
|
case (alu_opcode)
|
// BIT - Bit Test
|
// BIT - Bit Test
|
BIT_ZPG, BIT_ABS: begin
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BIT_ZPG, BIT_ABS: begin
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//result = A & alu_a;
|
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result = A & alu_a;
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result = A & alu_a;
|
end
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end
|
|
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// BRK - Force Interrupt
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// BRK - Force Interrupt
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//BRK_IMP: begin
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//BRK_IMP: begin
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// STATUS[B] = 1'b1;
|
// STATUS[B] = 1'b1;
|
//end
|
//end
|
|
|
// CLC - Clear Carry Flag
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// CLC - Clear Carry Flag
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//CLC_IMP: begin
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//CLC_IMP: begin
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// STATUS[C] = 1'b0;
|
// STATUS[C] = 1'b0;
|
//end
|
//end
|
|
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// CLD - Clear Decimal Flag
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// CLD - Clear Decimal Flag
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//CLD_IMP: begin
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//CLD_IMP: begin
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// STATUS[D] = 1'b0;
|
// STATUS[D] = 1'b0;
|
//end
|
//end
|
|
|
// CLI - Clear Interrupt Disable
|
// CLI - Clear Interrupt Disable
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//CLI_IMP: begin
|
//CLI_IMP: begin
|
// STATUS[I] = 1'b0;
|
// STATUS[I] = 1'b0;
|
//end
|
//end
|
|
|
// CLV - Clear Overflow Flag
|
// CLV - Clear Overflow Flag
|
//CLV_IMP: begin
|
//CLV_IMP: begin
|
// STATUS[V] = 1'b0;
|
// STATUS[V] = 1'b0;
|
//end
|
//end
|
|
|
// NOP - No Operation
|
// NOP - No Operation
|
//NOP_IMP: begin
|
//NOP_IMP: begin
|
// Do nothing :-D
|
// Do nothing :-D
|
//end
|
//end
|
|
|
// PLP - Pull Processor Status Register
|
// PLP - Pull Processor Status Register
|
// RTI - Return from Interrupt
|
// RTI - Return from Interrupt
|
//PLP_IMP, RTI_IMP: begin
|
//PLP_IMP, RTI_IMP: begin
|
// STATUS = alu_a;
|
// STATUS = alu_a;
|
//end
|
//end
|
|
|
PLA_IMP : begin
|
PLA_IMP : begin
|
result = alu_a;
|
result = alu_a;
|
end
|
end
|
|
|
// STA - Store Accumulator
|
// STA - Store Accumulator
|
// PHA - Push A
|
// PHA - Push A
|
// TAX - Transfer Accumulator to X
|
// TAX - Transfer Accumulator to X
|
// TAY - Transfer Accumulator to Y
|
// TAY - Transfer Accumulator to Y
|
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
|
TAX_IMP, TAY_IMP, PHA_IMP, STA_ZPG, STA_ZPX, STA_ABS, STA_ABX, STA_ABY, STA_IDX, STA_IDY : begin
|
//result = A;
|
|
result = A;
|
result = A;
|
end
|
end
|
|
|
// STX - Store X Register
|
// STX - Store X Register
|
// TXA - Transfer X to Accumulator
|
// TXA - Transfer X to Accumulator
|
// TXS - Transfer X to Stack pointer
|
// TXS - Transfer X to Stack pointer
|
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
|
STX_ZPG, STX_ZPY, STX_ABS, TXA_IMP, TXS_IMP : begin
|
//result = X;
|
|
result = alu_x;
|
result = alu_x;
|
end
|
end
|
|
|
// STY - Store Y Register
|
// STY - Store Y Register
|
// TYA - Transfer Y to Accumulator
|
// TYA - Transfer Y to Accumulator
|
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
|
STY_ZPG, STY_ZPX, STY_ABS, TYA_IMP : begin
|
//result = Y;
|
|
result = alu_y;
|
result = alu_y;
|
end
|
end
|
|
|
// SEC - Set Carry Flag
|
// SEC - Set Carry Flag
|
//SEC_IMP: begin
|
//SEC_IMP: begin
|
// STATUS[C] = 1'b1;
|
// STATUS[C] = 1'b1;
|
//end
|
//end
|
|
|
// SED - Set Decimal Flag
|
// SED - Set Decimal Flag
|
//SED_IMP: begin
|
//SED_IMP: begin
|
// STATUS[D] = 1'b1;
|
// STATUS[D] = 1'b1;
|
//end
|
//end
|
|
|
// SEI - Set Interrupt Disable
|
// SEI - Set Interrupt Disable
|
//SEI_IMP: begin
|
//SEI_IMP: begin
|
// STATUS[I] = 1'b1;
|
// STATUS[I] = 1'b1;
|
//end
|
//end
|
|
|
// INC - Increment memory
|
// INC - Increment memory
|
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
|
INC_ZPG, INC_ZPX, INC_ABS, INC_ABX : begin
|
result = alu_a + 1;
|
result = alu_a + 1;
|
end
|
end
|
|
|
// INX - Increment X Register
|
// INX - Increment X Register
|
INX_IMP: begin
|
INX_IMP: begin
|
//result = X + 1;
|
|
result = alu_x + 1;
|
result = alu_x + 1;
|
end
|
end
|
|
|
// INY - Increment Y Register
|
// INY - Increment Y Register
|
INY_IMP : begin
|
INY_IMP : begin
|
//result = Y + 1;
|
|
result = alu_y + 1;
|
result = alu_y + 1;
|
end
|
end
|
|
|
// DEC - Decrement memory
|
// DEC - Decrement memory
|
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
|
DEC_ZPG, DEC_ZPX, DEC_ABS, DEC_ABX : begin
|
result = alu_a - 1;
|
result = alu_a - 1;
|
end
|
end
|
|
|
// DEX - Decrement X register
|
// DEX - Decrement X register
|
DEX_IMP: begin
|
DEX_IMP: begin
|
//result = X - 1;
|
|
result = alu_x - 1;
|
result = alu_x - 1;
|
end
|
end
|
|
|
// DEY - Decrement Y Register
|
// DEY - Decrement Y Register
|
DEY_IMP: begin
|
DEY_IMP: begin
|
//result = Y - 1;
|
|
result = alu_y - 1;
|
result = alu_y - 1;
|
end
|
end
|
|
|
// ADC - Add with carry
|
// ADC - Add with carry
|
// TODO: verify synthesis for % operand
|
// TODO: verify synthesis for % operand
|
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
|
ADC_IMM, ADC_ZPG, ADC_ZPX, ADC_ABS, ADC_ABX, ADC_ABY, ADC_IDX, ADC_IDY : begin
|
if (alu_status[D] == 1) begin
|
if (alu_status[D] == 1) begin
|
//$display("MODO DECIMAL");
|
//$display("MODO DECIMAL");
|
//AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
//AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
|
//$display("op1[3:0] + op2[3:0] + alu_status[C]",op1[3:0], op2[3:0], alu_status[C]);
|
//AH = A[7:4] + alu_a[7:4];
|
//AH = A[7:4] + alu_a[7:4];
|
AH = op1[7:4] + op2[7:4];
|
AH = op1[7:4] + op2[7:4] + AL[4];
|
$display("AL = %d", AL);
|
//$display("op1[7:4] + op2[7:4] + AL[4]",op1[7:4], op2[7:4], AL[4]);
|
$display("AH = %d", AH);
|
if (AL > 9) bcdl = AL + 6;
|
if (AL > 9) begin
|
else bcdl = AL;
|
bcdh = AH + (AL / 10);
|
STATUS[Z] =
|
bcdl = AL % 10;
|
if (bcdh > 9)
|
end
|
bcdh2 = bcdh + 6;
|
else begin
|
else bcdh2 = bcdh;
|
bcdh = AH;
|
|
bcdl = AL;
|
|
end
|
|
|
|
// ok
|
|
|
|
if (bcdh > 9) begin
|
|
STATUS[C] = 1;
|
|
bcdh2 = bcdh % 10;
|
|
end
|
|
else begin
|
|
STATUS[C] = 0;
|
|
bcdh2 = bcdh;
|
|
end
|
|
//$display("bcdh2 = %d", bcdh2);
|
//$display("bcdh2 = %d", bcdh2);
|
//$display("bcdl = %d", bcdl);
|
//$display("bcdl = %d", bcdl);
|
|
STATUS[C] = AH[4];
|
result = {bcdh2[3:0],bcdl[3:0]};
|
result = {bcdh2[3:0],bcdl[3:0]};
|
end
|
end
|
else begin
|
else begin
|
//$display("MODO NORMAL");
|
//$display("MODO NORMAL");
|
{STATUS[C],result} = op1 + op2 + alu_status[C];
|
{STATUS[C],result} = op1 + op2 + alu_status[C];
|
end
|
end
|
|
|
if ((op1[7] == op2[7]) && (op1[7] != result[7]))
|
if ((op1[7] == op2[7]) && (op1[7] != result[7]))
|
STATUS[V] = 1;
|
STATUS[V] = 1;
|
else
|
else
|
STATUS[V] = 0;
|
STATUS[V] = 0;
|
end
|
end
|
|
|
// AND - Logical AND
|
// AND - Logical AND
|
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
|
AND_IMM, AND_ZPG, AND_ZPX, AND_ABS, AND_ABX, AND_ABY, AND_IDX, AND_IDY : begin
|
//result = A & alu_a;
|
|
result = A & alu_a;
|
result = A & alu_a;
|
end
|
end
|
|
|
// CMP - Compare
|
// CMP - Compare
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
|
CMP_IMM, CMP_ZPG, CMP_ZPX, CMP_ABS, CMP_ABX, CMP_ABY, CMP_IDX, CMP_IDY : begin
|
//result = A - alu_a;
|
|
result = A - alu_a;
|
result = A - alu_a;
|
//STATUS[C] = (A >= alu_a) ? 1 : 0;
|
|
STATUS[C] = (A >= alu_a) ? 1 : 0;
|
STATUS[C] = (A >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
// EOR - Exclusive OR
|
// EOR - Exclusive OR
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
|
EOR_IMM, EOR_ZPG, EOR_ZPX, EOR_ABS, EOR_ABX, EOR_ABY, EOR_IDX, EOR_IDY : begin
|
result = A ^ alu_a;
|
result = A ^ alu_a;
|
//result = A ^ alu_a;
|
|
//$display("op1 ^ op2 = result");
|
|
//$display("%d ^ %d = %d", op1, op2, result);
|
|
end
|
end
|
|
|
// LDA - Load Accumulator
|
// LDA - Load Accumulator
|
// LDX - Load X Register
|
// LDX - Load X Register
|
// LDY - Load Y Register
|
// LDY - Load Y Register
|
// TSX - Transfer Stack Pointer to X
|
// TSX - Transfer Stack Pointer to X
|
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
|
LDA_IMM, LDA_ZPG, LDA_ZPX, LDA_ABS, LDA_ABX, LDA_ABY, LDA_IDX, LDA_IDY,
|
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
|
LDX_IMM, LDX_ZPG, LDX_ZPY, LDX_ABS, LDX_ABY,
|
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
|
LDY_IMM, LDY_ZPG, LDY_ZPX, LDY_ABS, LDY_ABX,
|
TSX_IMP : begin
|
TSX_IMP : begin
|
result = alu_a;
|
result = alu_a;
|
end
|
end
|
|
|
// ORA - Logical OR
|
// ORA - Logical OR
|
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
|
ORA_IMM, ORA_ZPG, ORA_ZPX, ORA_ABS, ORA_ABX, ORA_ABY, ORA_IDX, ORA_IDY : begin
|
//result = A | alu_a;
|
//result = A | alu_a;
|
result = A | alu_a;
|
result = A | alu_a;
|
end
|
end
|
|
|
// SBC - Subtract with Carry
|
// SBC - Subtract with Carry
|
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
|
SBC_IMM, SBC_ZPG, SBC_ZPX, SBC_ABS, SBC_ABX, SBC_ABY, SBC_IDX, SBC_IDY : begin
|
if (alu_status[D] == 1) begin
|
if (alu_status[D] == 1) begin
|
/* //AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
/* //AL = A[3:0] + alu_a[3:0] + alu_status[C];
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
AL = op1[3:0] + op2[3:0] + alu_status[C];
|
//AH = A[7:4] + alu_a[7:4];
|
//AH = A[7:4] + alu_a[7:4];
|
AH = op1[7:4] + op2[7:4];
|
AH = op1[7:4] + op2[7:4];
|
if (AL > 9) begin
|
if (AL > 9) begin
|
bcdh = AH + (AL / 10);
|
bcdh = AH + (AL / 10);
|
bcdl = AL % 10;
|
bcdl = AL % 10;
|
end
|
end
|
else begin
|
else begin
|
bcdh = AH;
|
bcdh = AH;
|
bcdl = AL;
|
bcdl = AL;
|
end
|
end
|
if (bcdh > 9) begin
|
if (bcdh > 9) begin
|
STATUS[C] = 1;
|
STATUS[C] = 1;
|
bcdh2 = bcdh % 10;
|
bcdh2 = bcdh % 10;
|
end
|
end
|
else begin
|
else begin
|
STATUS[C] = 0;
|
STATUS[C] = 0;
|
bcdh2 = bcdh;
|
bcdh2 = bcdh;
|
end
|
end
|
result = {bcdh2[3:0],bcdl[3:0]};*/
|
result = {bcdh2[3:0],bcdl[3:0]};*/
|
//C := P_In(Flag_C) or not Op(0);
|
//C := P_In(Flag_C) or not Op(0);
|
AL = {op1[3:0],alu_status[C]} - {op2[3:0],1'b1};
|
AL = {op1[3:0],alu_status[C]} - {op2[3:0],1'b1};
|
AH = {op1[7:4],1'b0} - {op2[7:4],AL[5]};
|
AH = {op1[7:4],1'b0} - {op2[7:4],AL[5]};
|
|
|
if (AL[5] == 1) begin
|
if (AL[5] == 1) begin
|
bcdl[5:1] = AL[5:1] - 6;
|
bcdl[5:1] = AL[5:1] - 6;
|
end
|
end
|
AH = {op1[7:4],1'b0} - {op2[7:4],bcdl[6]};
|
AH = {op1[7:4],1'b0} - {op2[7:4],bcdl[6]};
|
if (AH[5] == 1) begin
|
if (AH[5] == 1) begin
|
bcdh[5:1] = AH[5:1] - 6;
|
bcdh[5:1] = AH[5:1] - 6;
|
end
|
end
|
result = {bcdh[4:1],bcdl[4:1]};
|
result = {bcdh[4:1],bcdl[4:1]};
|
STATUS[C] = ~result[7];
|
STATUS[C] = ~result[7];
|
end
|
end
|
else begin
|
else begin
|
op2 = ~op2;
|
op2 = ~op2;
|
//$display("MODO NORMAL");
|
//$display("MODO NORMAL");
|
result = op1 + op2 + alu_status[C];
|
result = op1 + op2 + alu_status[C];
|
STATUS[C] = ~result[7];
|
STATUS[C] = ~result[7];
|
end
|
end
|
/* if (alu_status[D] == 1) begin
|
/* if (alu_status[D] == 1) begin
|
bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
|
bcdl = op1[3:0] - op2[3:0] - (1 - alu_status[C]);
|
bcdh = op1[7:4] - op2[7:4];
|
bcdh = op1[7:4] - op2[7:4];
|
if (bcdl > 9) begin
|
if (bcdl > 9) begin
|
bcdh = bcdh + bcdl[5:4];
|
bcdh = bcdh + bcdl[5:4];
|
bcdl = bcdl % 10;
|
bcdl = bcdl % 10;
|
end
|
end
|
if (bcdh > 9) begin
|
if (bcdh > 9) begin
|
STATUS[C] = 1;
|
STATUS[C] = 1;
|
bcdh = bcdh % 10;
|
bcdh = bcdh % 10;
|
end
|
end
|
result = {bcdh[3:0],bcdl[3:0]};
|
result = {bcdh[3:0],bcdl[3:0]};
|
end
|
end
|
else begin
|
else begin
|
op2 = ~alu_a;
|
op2 = ~alu_a;
|
result = op1 + op2 + alu_status[C];
|
result = op1 + op2 + alu_status[C];
|
STATUS[C] = ~result[7];
|
STATUS[C] = ~result[7];
|
end
|
end
|
*/
|
*/
|
|
|
if ((op1[7] == sign) && (op1[7] != result[7]))
|
if ((op1[7] == sign) && (op1[7] != result[7]))
|
STATUS[V] = 1;
|
STATUS[V] = 1;
|
else
|
else
|
STATUS[V] = 0;
|
STATUS[V] = 0;
|
|
|
end
|
end
|
|
|
// ASL - Arithmetic Shift Left
|
// ASL - Arithmetic Shift Left
|
ASL_ACC : begin
|
ASL_ACC : begin
|
//{STATUS[C],result} = A << 1;
|
//{STATUS[C],result} = A << 1;
|
//{STATUS[C],result} = {A,1'b0};
|
//{STATUS[C],result} = {A,1'b0};
|
{STATUS[C],result} = {A,1'b0};
|
{STATUS[C],result} = {A,1'b0};
|
end
|
end
|
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
|
ASL_ZPG, ASL_ZPX, ASL_ABS, ASL_ABX : begin
|
//{STATUS[C],result} = alu_a << 1;
|
//{STATUS[C],result} = alu_a << 1;
|
{STATUS[C],result} = {alu_a,1'b0};
|
{STATUS[C],result} = {alu_a,1'b0};
|
end
|
end
|
|
|
// LSR - Logical Shift Right
|
// LSR - Logical Shift Right
|
LSR_ACC: begin
|
LSR_ACC: begin
|
//{result, STATUS[C]} = A >> 1;
|
//{result, STATUS[C]} = A >> 1;
|
//{result,STATUS[C]} = {1'b0,A};
|
//{result,STATUS[C]} = {1'b0,A};
|
{result,STATUS[C]} = {1'b0,A};
|
{result,STATUS[C]} = {1'b0,A};
|
end
|
end
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
LSR_ZPG, LSR_ZPX, LSR_ABS, LSR_ABX : begin
|
//{result, STATUS[C]} = alu_a >> 1;
|
//{result, STATUS[C]} = alu_a >> 1;
|
{result,STATUS[C]} = {1'b0,alu_a};
|
{result,STATUS[C]} = {1'b0,alu_a};
|
end
|
end
|
|
|
// ROL - Rotate Left
|
// ROL - Rotate Left
|
ROL_ACC : begin
|
ROL_ACC : begin
|
//{STATUS[C],result} = {A,alu_status[C]};
|
//{STATUS[C],result} = {A,alu_status[C]};
|
{STATUS[C],result} = {A,alu_status[C]};
|
{STATUS[C],result} = {A,alu_status[C]};
|
end
|
end
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
ROL_ZPG, ROL_ZPX, ROL_ABS, ROL_ABX : begin
|
{STATUS[C],result} = {alu_a,alu_status[C]};
|
{STATUS[C],result} = {alu_a,alu_status[C]};
|
end
|
end
|
|
|
// ROR - Rotate Right
|
// ROR - Rotate Right
|
ROR_ACC : begin
|
ROR_ACC : begin
|
//{result,STATUS[C]} = {alu_status[C],A};
|
//{result,STATUS[C]} = {alu_status[C],A};
|
{result,STATUS[C]} = {alu_status[C],A};
|
{result,STATUS[C]} = {alu_status[C],A};
|
end
|
end
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
ROR_ZPG, ROR_ZPX, ROR_ABS, ROR_ABX : begin
|
{result, STATUS[C]} = {alu_status[C], alu_a};
|
{result, STATUS[C]} = {alu_status[C], alu_a};
|
end
|
end
|
|
|
// CPX - Compare X Register
|
// CPX - Compare X Register
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
CPX_IMM, CPX_ZPG, CPX_ABS : begin
|
//result = X - alu_a;
|
//result = X - alu_a;
|
result = alu_x - alu_a;
|
result = alu_x - alu_a;
|
//STATUS[C] = (X >= alu_a) ? 1 : 0;
|
//STATUS[C] = (X >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_x >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
// CPY - Compare Y Register
|
// CPY - Compare Y Register
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
CPY_IMM, CPY_ZPG, CPY_ABS : begin
|
//result = Y - alu_a;
|
//result = Y - alu_a;
|
result = alu_y - alu_a;
|
result = alu_y - alu_a;
|
//STATUS[C] = (Y >= alu_a) ? 1 : 0;
|
//STATUS[C] = (Y >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
|
STATUS[C] = (alu_y >= alu_a) ? 1 : 0;
|
end
|
end
|
|
|
default: begin // NON-DEFAULT OPCODES FALL HERE
|
default: begin // NON-DEFAULT OPCODES FALL HERE
|
end
|
end
|
endcase
|
endcase
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[Z] = (result == 0) ? 1 : 0;
|
STATUS[N] = result[7];
|
STATUS[N] = result[7];
|
end
|
end
|
end
|
end
|
endmodule
|
endmodule
|
|
|
|
|
