////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// T6507LP IP Core ////
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//// T6507LP IP Core ////
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//// ////
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//// ////
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//// This file is part of the T6507LP project ////
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//// This file is part of the T6507LP project ////
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//// http://www.opencores.org/cores/t6507lp/ ////
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//// http://www.opencores.org/cores/t6507lp/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6507 FSM testbench ////
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//// 6507 FSM testbench ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Test indirect indexed mode ////
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//// - Test indirect indexed mode ////
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//// - Test absolute indirect mode ////
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//// - Test absolute indirect mode ////
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//// - Test special stack instructions ////
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//// - Test special stack instructions ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`timescale 1ns / 1ps
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module t6507lp_fsm_tb();
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module t6507lp_fsm_tb();
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reg clk;
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reg clk;
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reg reset_n;
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reg reset_n;
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reg [7:0] alu_result;
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reg [7:0] alu_result;
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reg [7:0] alu_status;
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reg [7:0] alu_status;
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reg [7:0] data_in;
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reg [7:0] data_in;
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reg [7:0] alu_x;
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reg [7:0] alu_x;
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reg [7:0] alu_y;
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reg [7:0] alu_y;
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wire [12:0] address;
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wire [12:0] address;
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wire control;
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wire control;
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wire [7:0] data_out;
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wire [7:0] data_out;
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wire [7:0] alu_opcode;
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wire [7:0] alu_opcode;
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wire [7:0] alu_a;
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wire [7:0] alu_a;
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wire alu_enable;
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wire alu_enable;
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integer my_i;
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integer my_i;
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`include "../T6507LP_Package.v" // TODO: remove this include
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`include "T6507LP_Package.v" // TODO: remove this include
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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t6507lp_fsm #(8,13) my_dut(clk, reset_n, alu_result, alu_status, data_in, address, control, data_out, alu_opcode, alu_a, alu_enable, alu_x, alu_y);
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always #10 clk = ~clk;
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always #10 clk = ~clk;
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reg[7:0] fake_mem[2**13-1:0];
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reg[7:0] fake_mem[2**13-1:0];
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initial begin
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initial begin
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clk = 0;
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clk = 0;
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reset_n = 1'b0;
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reset_n = 1'b0;
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alu_result = 8'h01;
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alu_result = 8'h01;
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alu_status = 8'h00;
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alu_status = 8'h00;
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alu_x = 8'h07;
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alu_x = 8'h07;
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alu_y = 8'h03;
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alu_y = 8'h03;
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for (my_i=0; my_i < 2**13; my_i= my_i+1) begin
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for (my_i=0; my_i < 2**13; my_i= my_i+1) begin
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$write("\n%d",my_i);
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$write("\n%d",my_i);
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fake_mem[my_i]=8'h00;
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fake_mem[my_i]=8'h00;
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end
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end
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[0] = ASL_ACC; // testing ACC mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[1] = ADC_IMM; // testing IMM mode
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fake_mem[2] = 8'h27;
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fake_mem[2] = 8'h27;
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[3] = JMP_ABS; // testing ABS mode, JMP type
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fake_mem[4] = 8'h09;
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fake_mem[4] = 8'h09;
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fake_mem[5] = 8'h00;
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fake_mem[5] = 8'h00;
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fake_mem[6] = ASL_ACC; // wont be executed
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fake_mem[6] = ASL_ACC; // wont be executed
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fake_mem[7] = ASL_ACC; // wont be executed
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fake_mem[7] = ASL_ACC; // wont be executed
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fake_mem[8] = ASL_ACC; // wont be executed
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fake_mem[8] = ASL_ACC; // wont be executed
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fake_mem[9] = ASL_ACC; // wont be executed
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fake_mem[9] = ASL_ACC; // wont be executed
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fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27)
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fake_mem[10] = LDA_ABS; // testing ABS mode, READ type. A = MEM[0002]. (a=27)
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fake_mem[11] = 8'h02;
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fake_mem[11] = 8'h02;
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fake_mem[12] = 8'h00;
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fake_mem[12] = 8'h00;
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fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC
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fake_mem[13] = ASL_ABS; // testing ABS mode, READ_MODIFY_WRITE type. should overwrite the first ASL_ACC
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fake_mem[14] = 8'h00;
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fake_mem[14] = 8'h00;
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fake_mem[15] = 8'h00;
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fake_mem[15] = 8'h00;
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fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1]
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fake_mem[16] = STA_ABS; // testing ABS mode, WRITE type. should write alu_result on MEM[1]
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fake_mem[17] = 8'h01;
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fake_mem[17] = 8'h01;
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fake_mem[18] = 8'h00;
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fake_mem[18] = 8'h00;
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fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type
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fake_mem[19] = LDA_ZPG; // testing ZPG mode, READ type
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fake_mem[20] = 8'h00;
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fake_mem[20] = 8'h00;
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fake_mem[21] = ASL_ZPG; // testing ZPG mode, READ_MODIFY_WRITE type
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fake_mem[21] = ASL_ZPG; // testing ZPG mode, READ_MODIFY_WRITE type
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fake_mem[22] = 8'h00;
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fake_mem[22] = 8'h00;
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fake_mem[23] = STA_ZPG; // testing ZPG mode, WRITE type
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fake_mem[23] = STA_ZPG; // testing ZPG mode, WRITE type
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fake_mem[24] = 8'h00;
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fake_mem[24] = 8'h00;
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fake_mem[25] = LDA_ZPX; // testing ZPX mode, READ type. A = MEM[x+1]
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fake_mem[25] = LDA_ZPX; // testing ZPX mode, READ type. A = MEM[x+1]
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fake_mem[26] = 8'h01;
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fake_mem[26] = 8'h01;
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fake_mem[27] = ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1;
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fake_mem[27] = ASL_ZPX; // testing ZPX mode, READ_MODIFY_WRITE type. MEM[x+1] = MEM[x+1] << 1;
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fake_mem[28] = 8'h01;
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fake_mem[28] = 8'h01;
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fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;
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fake_mem[29] = STA_ZPX; // testing ZPX mode, WRITE type. MEM[x+2] = A;
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fake_mem[30] = 8'h02;
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fake_mem[30] = 8'h02;
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fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed.
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fake_mem[31] = LDA_ABX; // testing ABX mode, READ TYPE. No page crossed.
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fake_mem[32] = 8'h0a;
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fake_mem[32] = 8'h0a;
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fake_mem[33] = 8'h00;
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fake_mem[33] = 8'h00;
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fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.
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fake_mem[34] = LDA_ABX; // testing ABX mode, READ TYPE. Page crossed.
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fake_mem[35] = 8'hff;
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fake_mem[35] = 8'hff;
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fake_mem[36] = 8'h00;
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fake_mem[36] = 8'h00;
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fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.
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fake_mem[37] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. No page crossed.
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fake_mem[38] = 8'h01;
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fake_mem[38] = 8'h01;
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fake_mem[39] = 8'd35;
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fake_mem[39] = 8'd35;
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fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
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fake_mem[40] = ASL_ABX; // testing ABX mode, READ_MODIFY_WRITE TYPE. Page crossed.
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fake_mem[41] = 8'hff;
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fake_mem[41] = 8'hff;
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fake_mem[42] = 8'h00;
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fake_mem[42] = 8'h00;
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fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed.
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fake_mem[40] = STA_ABX; // testing ABX mode, WRITE TYPE. No page crossed.
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fake_mem[41] = 8'h04;
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fake_mem[41] = 8'h04;
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fake_mem[42] = 8'h00;
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fake_mem[42] = 8'h00;
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fake_mem[43] = STA_ABX; // testing ABX mode, WRITE TYPE. Page crossed.
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fake_mem[43] = STA_ABX; // testing ABX mode, WRITE TYPE. Page crossed.
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fake_mem[44] = 8'hff;
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fake_mem[44] = 8'hff;
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fake_mem[45] = 8'h00;
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fake_mem[45] = 8'h00;
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fake_mem[46] = BNE_REL; // testing REL mode, taking a branch, no page crossed.
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fake_mem[46] = BNE_REL; // testing REL mode, taking a branch, no page crossed.
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fake_mem[47] = 8'h0a;
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fake_mem[47] = 8'h0a;
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fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
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fake_mem[58] = BNE_REL; // testing REL mode, taking a branch, page crossed.
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fake_mem[59] = 8'hff;
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fake_mem[59] = 8'hff;
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fake_mem[60] = 8'hff;
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fake_mem[60] = 8'hff;
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fake_mem[254] = 8'hff;
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fake_mem[254] = 8'hff;
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fake_mem[256] = 8'h55; // PCL fetched from here when executing RTS_IMP
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fake_mem[256] = 8'h55; // PCL fetched from here when executing RTS_IMP
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fake_mem[257] = 8'h01; // PCH fetched from here when executing RTS_IMP
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fake_mem[257] = 8'h01; // PCH fetched from here when executing RTS_IMP
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fake_mem[264] = 8'd340;
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fake_mem[264] = 8'd340;
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fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
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fake_mem[315] = BEQ_REL; // testing REL mode, not taking a branch, page would have crossed.
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fake_mem[316] = 8'hff;
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fake_mem[316] = 8'hff;
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fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
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fake_mem[317] = BEQ_REL; // testing REL mode, not taking a branch, page would not have crossed.
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fake_mem[318] = 8'h00;
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fake_mem[318] = 8'h00;
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fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed;
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fake_mem[319] = LDA_IDX; // testing IDX mode READ TYPE, no page crossed;
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fake_mem[320] = 8'h0a;
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fake_mem[320] = 8'h0a;
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fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed; this will actually do A = MEM[6] because there is no carry
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fake_mem[321] = LDA_IDX; // testing IDX mode READ TYPE, page crossed; this will actually do A = MEM[6] because there is no carry
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fake_mem[322] = 8'hff;
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fake_mem[322] = 8'hff;
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//fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE
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//fake_mem[319] = SLO_IDX; // testing IDX mode READ_MODIFY_WRITE TYPE
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//fake_mem[320] = 8'h0a; // all of read modify write instructions are not documented therefore will not be simulated
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//fake_mem[320] = 8'h0a; // all of read modify write instructions are not documented therefore will not be simulated
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fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
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fake_mem[323] = STA_IDX; // testing IDX mode WRITE TYPE, page crossed being ignored
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fake_mem[324] = 8'hff;
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fake_mem[324] = 8'hff;
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fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
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fake_mem[325] = STA_IDX; // testing IDX mode WRITE TYPE, page not crossed;
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fake_mem[326] = 8'h00;
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fake_mem[326] = 8'h00;
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fake_mem[327] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed;
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fake_mem[327] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed;
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fake_mem[328] = 8'h00;
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fake_mem[328] = 8'h00;
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fake_mem[329] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed.
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fake_mem[329] = LDA_IDY; // testing IDY mode READ TYPE, page not crossed but pointer overflowed.
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fake_mem[330] = 8'hff;
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fake_mem[330] = 8'hff;
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/* testing IDY mode READ TYPE, page crossed.
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/* testing IDY mode READ TYPE, page crossed.
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address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
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address may assume a invalid value when page is crossed but it is fixed on the next cycle when the true read occurs.
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this is probably not an issue */
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this is probably not an issue */
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fake_mem[331] = LDA_IDY;
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fake_mem[331] = LDA_IDY;
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fake_mem[332] = 8'hfe;
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fake_mem[332] = 8'hfe;
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fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
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fake_mem[333] = STA_IDY; // testing IDY mode WRITE TYPE, page crossed;
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fake_mem[334] = 8'h00;
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fake_mem[334] = 8'h00;
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fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
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fake_mem[335] = STA_IDY; // testing IDY mode WRITE TYPE, page not crossed;
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fake_mem[336] = 8'h0e;
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fake_mem[336] = 8'h0e;
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fake_mem[337] = INX_IMP;
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fake_mem[337] = INX_IMP;
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//fake_mem[338] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
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//fake_mem[338] = JMP_IND; // testing absolute indirect addressing. page crossed when updating pointer.
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//fake_mem[339] = 8'hff;
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//fake_mem[339] = 8'hff;
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//fake_mem[340] = 8'h00;
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//fake_mem[340] = 8'h00;
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//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
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//fake_mem[337] = JMP_IND; // testing absolute indirect addressing. no page crossed when updating pointer.
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//fake_mem[338] = 8'h3b; // these are commented cause they will actually jump
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//fake_mem[338] = 8'h3b; // these are commented cause they will actually jump
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//fake_mem[339] = 8'h00;
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//fake_mem[339] = 8'h00;
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//fake_mem[338] = BRK_IMP;
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//fake_mem[338] = BRK_IMP;
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//fake_mem[339] = RTI_IMP;
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//fake_mem[339] = RTI_IMP;
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//fake_mem[340] = RTS_IMP;
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//fake_mem[340] = RTS_IMP;
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// 341 is skipped due to RTS internal functionality
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// 341 is skipped due to RTS internal functionality
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//fake_mem[342] = PHA_IMP;
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//fake_mem[342] = PHA_IMP;
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//fake_mem[343] = PHP_IMP;
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//fake_mem[343] = PHP_IMP;
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//fake_mem[344] = PLA_IMP;
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//fake_mem[344] = PLA_IMP;
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//fake_mem[345] = PLP_IMP;
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//fake_mem[345] = PLP_IMP;
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fake_mem[338] = JSR_ABS;
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fake_mem[338] = JSR_ABS;
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fake_mem[339] = 8'h01;
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fake_mem[339] = 8'h01;
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fake_mem[340] = 8'h01;
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fake_mem[340] = 8'h01;
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fake_mem[8190] = 8'h53; // this is the reset vector
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fake_mem[8190] = 8'h53; // this is the reset vector
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fake_mem[8191] = 8'h01;
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fake_mem[8191] = 8'h01;
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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#4000;
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#4000;
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$finish; // to shut down the simulation
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$finish; // to shut down the simulation
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end //initial
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end //initial
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always @(clk) begin
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always @(clk) begin
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if (control == 0) begin // MEM_READ
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if (control == 0) begin // MEM_READ
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data_in <= fake_mem[address];
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data_in <= fake_mem[address];
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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end
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end
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else if (control == 1'b1) begin // MEM_WRITE
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else if (control == 1'b1) begin // MEM_WRITE
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fake_mem[address] <= data_out;
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fake_mem[address] <= data_out;
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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$write("\nreading from mem position %h: %h", address, fake_mem[address]);
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end
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end
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end
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end
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endmodule
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endmodule
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