////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// T6532 IP Core ////
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//// T6532 IP Core ////
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//// ////
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//// ////
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//// This file is part of the T2600 project ////
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//// This file is part of the T2600 project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// 6532 testbench ////
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//// 6532 testbench ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module t6532_tb();
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module t6532_tb();
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// mem_rw signals
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// mem_rw signals
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localparam MEM_READ = 1'b0;
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localparam MEM_READ = 1'b0;
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localparam MEM_WRITE = 1'b1;
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localparam MEM_WRITE = 1'b1;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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reg clk; // regs are inputs
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reg clk; // regs are inputs
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reg reset_n;
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reg reset_n;
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reg [15:0] io_lines;
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reg [15:0] io_lines;
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reg enable;
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reg enable;
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reg mem_rw;
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reg mem_rw;
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reg [ADDR_SIZE_:0] address;
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reg [ADDR_SIZE_:0] address;
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reg [DATA_SIZE_:0] data_drv;
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reg [DATA_SIZE_:0] data_drv;
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tri [DATA_SIZE_:0] data = data_drv;
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tri [DATA_SIZE_:0] data = data_drv;
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t6532 #(DATA_SIZE, ADDR_SIZE) t6532(
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t6532 #(DATA_SIZE, ADDR_SIZE) t6532(
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.clk (clk),
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.clk (clk),
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.reset_n (reset_n),
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.reset_n (reset_n),
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.io_lines (io_lines),
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.io_lines (io_lines),
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.enable (enable),
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.enable (enable),
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.mem_rw (mem_rw),
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.mem_rw (mem_rw),
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.address (address),
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.address (address),
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.data (data)
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.data (data)
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);
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);
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always #10 clk = ~clk;
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always #10 clk = ~clk;
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always @(*) begin
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always @(*) begin
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if (mem_rw == MEM_READ) begin
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if (mem_rw == MEM_READ) begin
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data_drv = 8'hZ;
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data_drv = 8'hZ;
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end
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end
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end
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end
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initial begin
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initial begin
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clk = 1'b0;
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clk = 1'b0;
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reset_n = 1'b0;
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reset_n = 1'b0;
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io_lines = 15'd0;
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io_lines = 16'd0;
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enable = 1'b0;
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enable = 1'b0;
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mem_rw = MEM_READ;
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mem_rw = MEM_READ;
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address = 0;
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address = 0;
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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@(negedge clk) // will wait for next negative edge of the clock (t=20)
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reset_n=1'b1;
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reset_n=1'b1;
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@(negedge clk) // testing the port_b. all switches must change!
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io_lines = 16'h00FF;
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@(negedge clk) // testing the port_b. all switches must change!
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io_lines = 16'h00FF;
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@(negedge clk) // testing the port_a. all switches must change since ddra = 0. (0 == input)
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io_lines = 16'hFF00;
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@(negedge clk) // setting ddra = FF. (output)
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enable = 1'b1;
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io_lines = 16'hFF00;
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address = 10'h281;
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mem_rw = MEM_WRITE;
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data_drv = 8'hFF;
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@(negedge clk) // testing port_a again. no switching this time!
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enable = 1'b0;
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io_lines = 16'h0000;
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address = 0;
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mem_rw = MEM_READ;
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@(negedge clk) // writing at the memory
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enable = 1'b1;
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address = 10'd255;
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mem_rw = MEM_WRITE;
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data_drv = 8'h11;
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@(negedge clk) // reading memory (output)
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enable = 1'b1;
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address = 10'd255;
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mem_rw = MEM_READ;
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@(negedge clk) // using the timer to count 100*1 cycle.
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enable = 1'b1;
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address = 10'h294;
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mem_rw = MEM_WRITE;
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data_drv = 8'd100;
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@(negedge clk);
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mem_rw = MEM_READ;
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enable = 1'b0;
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#2040;
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@(negedge clk) // using the timer to count 10*8 cycles.
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enable = 1'b1;
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address = 10'h295;
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mem_rw = MEM_WRITE;
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data_drv = 8'd10;
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@(negedge clk);
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mem_rw = MEM_READ;
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enable = 1'b0;
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#1640;
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#4000;
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$finish; // to shut down the simulation
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$finish; // to shut down the simulation
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end //initial
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end //initial
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endmodule
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endmodule
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