////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// t2600 IP Core ////
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//// t2600 IP Core ////
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//// ////
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//// ////
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//// This file is part of the t2600 project ////
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//// This file is part of the t2600 project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// VGA controller ////
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//// VGA controller ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Feed the controller with data ////
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//// - Feed the controller with data ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module vga_controller ( reset_n, clk_50, pixel, vert_counter, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, clk_358);
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module vga_controller ( reset_n, clk_50, pixel, read_data, SW, VGA_R, VGA_G, VGA_B, LEDR, VGA_VS, VGA_HS, read_addr);
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input reset_n;
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input reset_n;
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input clk_50;
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input clk_50;
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input [8:0] SW;
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input [8:0] SW;
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input [11:0] pixel;
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input [2:0] pixel;
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input [4:0] vert_counter;
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input [2:0] read_data;
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output reg [3:0] VGA_R;
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output reg [3:0] VGA_R;
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output reg [3:0] VGA_G;
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output reg [3:0] VGA_G;
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output reg [3:0] VGA_B;
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output reg [3:0] VGA_B;
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output [9:0] LEDR;
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output [9:0] LEDR;
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output reg VGA_VS;
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output reg VGA_VS;
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output reg VGA_HS;
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output reg VGA_HS;
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input clk_358;
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output reg [10:0] read_addr;
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reg clk_25;
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reg clk_25;
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reg [9:0] hc;
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reg [9:0] hc;
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reg [9:0] vc;
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reg [9:0] vc;
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reg vsenable;
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reg vsenable;
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wire vidon;
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wire vidon;
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reg [11:0] vid_data;
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assign LEDR[8:0] = SW;
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assign LEDR[8:0] = SW;
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assign LEDR[9] = reset_n;
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assign LEDR[9] = reset_n;
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always @ (posedge clk_50 or negedge reset_n)
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always @ (posedge clk_50 or negedge reset_n)
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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clk_25 <= 0;
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clk_25 <= 0;
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end
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end
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else begin
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else begin
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clk_25 <= !clk_25;
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clk_25 <= !clk_25;
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end
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end
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end
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end
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always @ (posedge clk_25 or negedge reset_n)
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always @ (posedge clk_25 or negedge reset_n)
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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hc <= 0;
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hc <= 0;
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VGA_HS <= 1;
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VGA_HS <= 1;
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vsenable <= 0;
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vsenable <= 0;
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end
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end
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else if (hc < 640) begin
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else if (hc < 640) begin
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hc <= hc + 1;
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hc <= hc + 1;
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vsenable <= 0;
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vsenable <= 0;
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VGA_HS <= 1;
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VGA_HS <= 1;
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end
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end
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else if (hc < 640 + 16) begin
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else if (hc < 640 + 16) begin
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VGA_HS <= 1;
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VGA_HS <= 1;
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hc <= hc + 1;
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hc <= hc + 1;
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vsenable <= 0;
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vsenable <= 0;
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end
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end
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else if (hc < 640 + 16 + 96) begin
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else if (hc < 640 + 16 + 96) begin
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VGA_HS <= 0;
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VGA_HS <= 0;
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hc <= hc + 1;
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hc <= hc + 1;
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vsenable <= 0;
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vsenable <= 0;
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end
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end
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else if (hc < 640 + 16 + 96 + 48) begin
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else if (hc < 640 + 16 + 96 + 48) begin
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VGA_HS <= 1;
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VGA_HS <= 1;
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hc <= hc + 1;
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hc <= hc + 1;
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vsenable <= 0;
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vsenable <= 0;
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end
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end
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else begin
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else begin
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VGA_HS <= 1;
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VGA_HS <= 1;
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hc <= 0;
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hc <= 0;
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vsenable <= 1;
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vsenable <= 1;
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end
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end
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end
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end
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always @ (posedge clk_25 or negedge reset_n)
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always @ (posedge clk_25 or negedge reset_n)
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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vc <= 0;
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vc <= 0;
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VGA_VS <= 1;
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VGA_VS <= 1;
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end
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end
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else begin
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else begin
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if (vsenable == 1) begin
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if (vsenable == 1) begin
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vc <= vc + 1;
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vc <= vc + 1;
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end
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end
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if (vc < 480) begin
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if (vc < 480) begin
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VGA_VS <= 1;
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VGA_VS <= 1;
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end
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end
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else if (vc < 480 + 11) begin
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else if (vc < 480 + 11) begin
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VGA_VS <= 1;
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VGA_VS <= 1;
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end
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end
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else if (vc < 480 + 11 + 2) begin
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else if (vc < 480 + 11 + 2) begin
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VGA_VS <= 0;
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VGA_VS <= 0;
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end
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end
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else if (vc < 480 + 11 + 2 + 31) begin
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else if (vc < 480 + 11 + 2 + 31) begin
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VGA_VS <= 1;
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VGA_VS <= 1;
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end
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end
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else begin
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else begin
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vc <= 0;
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vc <= 0;
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VGA_VS <= 1;
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VGA_VS <= 1;
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end
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end
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end
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end
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end
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end
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reg [11:0] pixel_reg;
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always @ (posedge clk_358 or negedge reset_n) begin
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if (!reset_n) begin
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pixel_reg <= 12'd0;
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end
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else begin
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pixel_reg <= pixel;
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end
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end
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always @ (posedge clk_25) begin
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always @ (posedge clk_25) begin
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//if (reset_n == 1'b0) begin
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VGA_R[0] <= 0;
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VGA_R[0] <= 0;
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VGA_G[0] <= 0;
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VGA_G[0] <= 0;
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VGA_B[0] <= 0;
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VGA_B[0] <= 0;
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VGA_R[1] <= 0;
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VGA_R[1] <= 0;
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VGA_G[1] <= 0;
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VGA_G[1] <= 0;
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VGA_B[1] <= 0;
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VGA_B[1] <= 0;
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VGA_R[2] <= 0;
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VGA_R[2] <= 0;
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VGA_G[2] <= 0;
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VGA_G[2] <= 0;
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VGA_B[2] <= 0;
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VGA_B[2] <= 0;
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VGA_R[3] <= 0;
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VGA_R[3] <= 0;
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VGA_G[3] <= 0;
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VGA_G[3] <= 0;
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VGA_B[3] <= 0;
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VGA_B[3] <= 0;
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//end
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//else
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if (vidon == 1) begin
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if (vidon == 1) begin
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VGA_R[0] <= pixel_reg[0];
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if (hc < 480 && vc < 400) begin
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VGA_R[1] <= pixel_reg[1];
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VGA_R[0] <= vid_data[0];
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VGA_R[2] <= pixel_reg[2];
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VGA_R[1] <= vid_data[1];
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VGA_R[3] <= pixel_reg[3];
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VGA_R[2] <= vid_data[2];
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VGA_G[0] <= pixel_reg[4];
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VGA_R[3] <= vid_data[3];
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VGA_G[1] <= pixel_reg[5];
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VGA_G[0] <= vid_data[4];
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VGA_G[2] <= pixel_reg[6];
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VGA_G[1] <= vid_data[5];
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VGA_G[3] <= pixel_reg[7];
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VGA_G[2] <= vid_data[6];
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VGA_B[0] <= pixel_reg[8];
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VGA_G[3] <= vid_data[7];
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VGA_B[1] <= pixel_reg[9];
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VGA_B[0] <= vid_data[8];
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VGA_B[2] <= pixel_reg[10];
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VGA_B[1] <= vid_data[9];
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VGA_B[3] <= pixel_reg[11];
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VGA_B[2] <= vid_data[10];
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VGA_B[3] <= vid_data[11];
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end
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end
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end
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always @ (*) begin
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if (hc < 400 && vc < 480) begin
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read_addr = hc/10 + (vc/10)*48;
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//case (read_data)
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// default: begin
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vid_data = 12'd10;
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// end
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//endcase
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end
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else begin
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read_addr = 10'd0;
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vid_data = 12'b101010101010;
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end
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end
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end
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end
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assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
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assign vidon = (hc < 640 && vc < 480) ? 1 : 0;
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endmodule
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endmodule
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