////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// t2600 IP Core ////
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//// t2600 IP Core ////
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//// ////
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//// ////
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//// This file is part of the t2600 project ////
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//// This file is part of the t2600 project ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// http://www.opencores.org/cores/t2600/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Video module ////
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//// Video module ////
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//// ////
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//// ////
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//// TODO: ////
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//// TODO: ////
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//// - Everything? ////
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//// - Everything? ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Gabriel Oshiro Zardo, gabrieloshiro@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// - Samuel Nascimento Pagliarini (creep), snpagliarini@gmail.com ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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`include "timescale.v"
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data);
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module video(clk, reset_n, io_lines, enable, mem_rw, address, data);
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] DATA_SIZE = 4'd8;
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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parameter [3:0] ADDR_SIZE = 4'd10; // this is the *local* addr_size
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] DATA_SIZE_ = DATA_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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localparam [3:0] ADDR_SIZE_ = ADDR_SIZE - 4'd1;
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input clk; // master clock signal, 1.19mhz
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input clk; // master clock signal, 1.19mhz
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input reset_n;
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input reset_n;
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input [15:0] io_lines; // inputs from the keyboard controller
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input [15:0] io_lines; // inputs from the keyboard controller
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input enable; // since the address bus is shared an enable signal is used
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input enable; // since the address bus is shared an enable signal is used
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input mem_rw; // read == 0, write == 1
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input mem_rw; // read == 0, write == 1
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input [ADDR_SIZE_:0] address; // system address bus
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input [ADDR_SIZE_:0] address; // system address bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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inout [DATA_SIZE_:0] data; // controler <=> riot data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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reg [DATA_SIZE_:0] data_drv; // wrapper for the data bus
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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assign data = (mem_rw || !reset_n) ? 8'bZ : data_drv; // if under writing the bus receives the data from cpu, else local data.
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reg VSYNC; // vertical sync set-clear
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reg VSYNC; // vertical sync set-clear
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reg [2:0] VBLANK; // vertical blank set-clear
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reg [2:0] VBLANK; // vertical blank set-clear
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reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
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reg WSYNC; // s t r o b e wait for leading edge of horizontal blank
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg RSYNC; // s t r o b e reset horizontal sync counter
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reg [5:0] NUSIZ0; // number-size player-missile 0
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reg [5:0] NUSIZ0; // number-size player-missile 0
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reg [5:0] NUSIZ1; // number-size player-missile 1
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reg [5:0] NUSIZ1; // number-size player-missile 1
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reg [6:0] COLUP0; // color-lum player 0
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reg [6:0] COLUP0; // color-lum player 0
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reg [6:0] COLUP1; // color-lum player 1
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reg [6:0] COLUP1; // color-lum player 1
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reg [6:0] COLUPF; // color-lum playfield
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reg [6:0] COLUPF; // color-lum playfield
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reg [6:0] COLUBK; // color-lum background
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reg [6:0] COLUBK; // color-lum background
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reg [4:0] CTRLPF; // control playfield ball size & collisions
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reg [4:0] CTRLPF; // control playfield ball size & collisions
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reg REFP0; // reflect player 0
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reg REFP0; // reflect player 0
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reg REFP1; // reflect player 1
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reg REFP1; // reflect player 1
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reg [3:0] PF0; // playfield register byte 0
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reg [3:0] PF0; // playfield register byte 0
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reg [7:0] PF1; // playfield register byte 1
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reg [7:0] PF1; // playfield register byte 1
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reg [7:0] PF2; // playfield register byte 2
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reg [7:0] PF2; // playfield register byte 2
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reg RESP0; // s t r o b e reset player 0
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reg RESP0; // s t r o b e reset player 0
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reg RESP1; // s t r o b e reset player 1
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reg RESP1; // s t r o b e reset player 1
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reg RESM0; // s t r o b e reset missile 0
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reg RESM0; // s t r o b e reset missile 0
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reg RESM1; // s t r o b e reset missile 1
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reg RESM1; // s t r o b e reset missile 1
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reg RESBL; // s t r o b e reset ball
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reg RESBL; // s t r o b e reset ball
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reg [3:0] AUDC0; // audio control 0
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reg [3:0] AUDC0; // audio control 0
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reg [4:0] AUDC1; // audio control 1
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reg [4:0] AUDC1; // audio control 1
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reg [4:0] AUDF0; // audio frequency 0
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reg [4:0] AUDF0; // audio frequency 0
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reg [3:0] AUDF1; // audio frequency 1
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reg [3:0] AUDF1; // audio frequency 1
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reg [3:0] AUDV0; // audio volume 0
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reg [3:0] AUDV0; // audio volume 0
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reg [3:0] AUDV1; // audio volume 1
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reg [3:0] AUDV1; // audio volume 1
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reg [7:0] GRP0; // graphics player 0
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reg [7:0] GRP0; // graphics player 0
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reg [7:0] GRP1; // graphics player 1
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reg [7:0] GRP1; // graphics player 1
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reg ENAM0; // graphics (enable) missile 0
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reg ENAM0; // graphics (enable) missile 0
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reg ENAM1; // graphics (enable) missile 1
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reg ENAM1; // graphics (enable) missile 1
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reg ENABL; // graphics (enable) ball
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reg ENABL; // graphics (enable) ball
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reg [3:0] HMP0; // horizontal motion player 0
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reg [3:0] HMP0; // horizontal motion player 0
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reg [3:0] HMP1; // horizontal motion player 1
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reg [3:0] HMP1; // horizontal motion player 1
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reg [3:0] HMM0; // horizontal motion missile 0
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reg [3:0] HMM0; // horizontal motion missile 0
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reg [3:0] HMM1; // horizontal motion missile 1
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reg [3:0] HMM1; // horizontal motion missile 1
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reg [3:0] HMBL; // horizontal motion ball
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reg [3:0] HMBL; // horizontal motion ball
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reg VDELP0; // vertical delay player 0
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reg VDELP0; // vertical delay player 0
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reg VDEL01; // vertical delay player 1
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reg VDEL01; // vertical delay player 1
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reg VDELBL; // vertical delay ball
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reg VDELBL; // vertical delay ball
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reg RESMP0; // reset missile 0 to player 0
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reg RESMP0; // reset missile 0 to player 0
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reg RESMP1; // reset missile 1 to player 1
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reg RESMP1; // reset missile 1 to player 1
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reg HMOVE; // s t r o b e apply horizontal motion
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reg HMOVE; // s t r o b e apply horizontal motion
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reg HMCLR; // s t r o b e clear horizontal motion registers
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reg HMCLR; // s t r o b e clear horizontal motion registers
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reg CXCLR ; // s t r o b e clear collision latches
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reg CXCLR ; // s t r o b e clear collision latches
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reg [1:0] CXM0P; // read collision MO P1 M0 P0
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reg [1:0] CXM0P; // read collision MO P1 M0 P0
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reg [1:0] CXM1P; // read collision M1 P0 M1 P1
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reg [1:0] CXM1P; // read collision M1 P0 M1 P1
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reg [1:0] CXP0FB; // read collision P0 PF P0 BL
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reg [1:0] CXP0FB; // read collision P0 PF P0 BL
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reg [1:0] CXP1FB; // read collision P1 PF P1 BL
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reg [1:0] CXP1FB; // read collision P1 PF P1 BL
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reg [1:0] CXM0FB; // read collision M0 PF M0 BL
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reg [1:0] CXM0FB; // read collision M0 PF M0 BL
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reg [1:0] CXM1FB; // read collision M1 PF M1 BL
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reg [1:0] CXM1FB; // read collision M1 PF M1 BL
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reg CXBLPF; // read collision BL PF unused
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reg CXBLPF; // read collision BL PF unused
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reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
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reg [1:0] CXPPMM; // read collision P0 P1 M0 M1
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reg INPT0; // read pot port
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reg INPT0; // read pot port
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reg INPT1; // read pot port
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reg INPT1; // read pot port
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reg INPT2; // read pot port
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reg INPT2; // read pot port
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reg INPT3; // read pot port
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reg INPT3; // read pot port
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reg INPT4; // read input
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reg INPT4; // read input
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reg INPT5; // read input
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reg INPT5; // read input
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always @(posedge clk or negedge reset_n) begin
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always @(posedge clk or negedge reset_n) begin
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if (reset_n == 1'b0) begin
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if (reset_n == 1'b0) begin
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data_drv <= 8'h00;
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data_drv <= 8'h00;
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end
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end
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else begin
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else begin
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if (mem_rw == 1'b0) begin // reading!
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if (mem_rw == 1'b0) begin // reading!
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case (address)
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case (address)
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6'h00: data_drv <= {CXM0P, 6'b000000};
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6'h00: data_drv <= {CXM0P, 6'b000000};
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6'h01: data_drv <= {CXM1P, 6'b000000};
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6'h01: data_drv <= {CXM1P, 6'b000000};
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6'h02: data_drv <= {CXP0FB, 6'b000000};
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6'h02: data_drv <= {CXP0FB, 6'b000000};
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6'h03: data_drv <= {CXP1FB, 6'b000000};
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6'h03: data_drv <= {CXP1FB, 6'b000000};
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6'h04: data_drv <= {CXM0FB, 6'b000000};
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6'h04: data_drv <= {CXM0FB, 6'b000000};
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6'h05: data_drv <= {CXM1FB, 6'b000000};
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6'h05: data_drv <= {CXM1FB, 6'b000000};
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6'h06: data_drv <= {CXBLPF, 7'b000000};
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6'h06: data_drv <= {CXBLPF, 7'b000000};
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6'h07: data_drv <= {CXPPMM, 6'b000000};
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6'h07: data_drv <= {CXPPMM, 6'b000000};
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6'h08: data_drv <= {INPT0, 7'b000000};
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6'h08: data_drv <= {INPT0, 7'b000000};
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6'h09: data_drv <= {INPT1, 7'b000000};
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6'h09: data_drv <= {INPT1, 7'b000000};
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6'h0A: data_drv <= {INPT2, 7'b000000};
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6'h0A: data_drv <= {INPT2, 7'b000000};
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6'h0B: data_drv <= {INPT3, 7'b000000};
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6'h0B: data_drv <= {INPT3, 7'b000000};
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6'h0C: data_drv <= {INPT4, 7'b000000};
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6'h0C: data_drv <= {INPT4, 7'b000000};
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6'h0D: data_drv <= {INPT5, 7'b000000};
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6'h0D: data_drv <= {INPT5, 7'b000000};
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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else begin // writing!
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else begin // writing!
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case (address)
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case (address)
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6'h00: begin
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6'h00: begin
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VSYNC <= data;
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VSYNC <= data[1];
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end
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end
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6'h01: begin
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6'h01: begin
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VBLANK <= data;
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VBLANK <= {data[7:6], data[1]};
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end
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end
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6'h02: begin
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6'h02: begin
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WSYNC <= data;
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WSYNC <= 1'b1; // STROBE
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end
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end
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6'h03: begin
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6'h03: begin
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RSYNC <= data;
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RSYNC <= 1'b1; // STROBE
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end
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end
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6'h04: begin
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6'h04: begin
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NUSIZ0 <= data;
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NUSIZ0 <= data[5:0];
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end
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end
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6'h05: begin
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6'h05: begin
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NUSIZ1 <= data;
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NUSIZ1 <= data[5:0];
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end
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end
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6'h06: begin
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6'h06: begin
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COLUP0 <= data;
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COLUP0 <= data[7:1];
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end
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end
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6'h07: begin
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6'h07: begin
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COLUP1 <= data;
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COLUP1 <= data[7:1];
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end
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end
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6'h08: begin
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6'h08: begin
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COLUPF <= data;
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COLUPF <= data[7:1];
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end
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end
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6'h09: begin
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6'h09: begin
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COLUBK <= data;
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COLUBK <= data[7:1];
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end
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end
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6'h0a: begin
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6'h0a: begin
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CTRLPF <= data;
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CTRLPF <= {data[5:4], data[2:0]};
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end
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end
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6'h0b: begin
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6'h0b: begin
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NUSIZ1 <= data;
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REFP0 <= data[3];
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end
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end
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6'h0c: begin
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6'h0c: begin
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NUSIZ1 <= data;
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REFP1 <= data[3];
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end
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end
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6'h0d: begin
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PF0 <= data[7:4 ];
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end
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6'h0e: begin
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PF1 <= data;
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end
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6'h0f: begin
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PF2 <= data;
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end
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6'h10: begin
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RESP0 <= 1'b1; // STROBE
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end
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6'h11: begin
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RESP1 <= 1'b1; // STROBE
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end
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6'h12: begin
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RESM0 <= 1'b1; // STROBE
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end
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6'h13: begin
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RESM1 <= 1'b1; // STROBE
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end
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6'h14: begin
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RESBL <= 1'b1; // STROBE
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end
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6'h15: begin
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AUDC0 <= data[3:0];
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end
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6'h16: begin
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AUDC1 <= data[4:0];
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end
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6'h17: begin
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AUDF0 <= data[4:0];
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end
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6'h18: begin
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AUDF1 <= data[3:0];
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end
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6'h19: begin
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AUDV0 <= data[3:0];
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end
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6'h1A: begin
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AUDV1 <= data[3:0];
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end
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6'h1B: begin
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GRP0 <= data;
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end
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6'h1C: begin
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GRP1 <= data;
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end
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6'h1D: begin
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ENAM0 <= data[1];
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end
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6'h1E: begin
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ENAM1 <= data[1];
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end
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6'h1F: begin
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ENABL <= data[1];
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end
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6'h20: begin
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HMP0 <= data[7:4];
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end
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6'h21: begin
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HMP1 <= data[7:4];
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end
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6'h22: begin
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HMM0 <= data[7:4];
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end
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6'h23: begin
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HMM1 <= data[7:4];
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end
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6'h24: begin
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HMBL <= data[7:4];
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end
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6'h25: begin
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VDELP0 <= data[0];
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end
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6'h26: begin
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VDEL01 <= data[0];
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end
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6'h27: begin
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VDELBL <= data[0];
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end
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6'h28: begin
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RESMP0 <= data[1];
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end
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6'h29: begin
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RESMP1 <= data[1];
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end
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6'h2a: begin
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HMOVE <= 1'b1; // STROBE
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end
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6'h2b: begin
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HMCLR <= 1'b1; // STROBE
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end
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6'h2c: begin
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CXCLR <= 1'b1; // STROBE
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end
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default: begin
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default: begin
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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