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[/] [t6507lp/] [trunk/] [sim/] [T6507LP_ULA/] [T6507LP_ALU_TestBench.v] - Diff between revs 81 and 113
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module T6507LP_ALU_TestBench(input dummy,output error);
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module T6507LP_ALU_TestBench(input dummy,output error);
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`include "T6507LP_Package.v"
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`include "T6507LP_Package.v"
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reg clk_i;
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reg clk_i;
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reg n_rst_i;
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reg n_rst_i;
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reg alu_enable;
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reg alu_enable;
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wire [7:0] alu_result;
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wire [7:0] alu_result;
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wire [7:0] alu_status;
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wire [7:0] alu_status;
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reg [7:0] alu_opcode;
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reg [7:0] alu_opcode;
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reg [7:0] alu_a;
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reg [7:0] alu_a;
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//`include "T6507LP_Package.v"
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//`include "T6507LP_Package.v"
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T6507LP_ALU DUT (
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T6507LP_ALU DUT (
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.clk_i (clk_i),
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.clk_i (clk_i),
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.n_rst_i (n_rst_i),
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.n_rst_i (n_rst_i),
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.alu_enable (alu_enable),
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.alu_enable (alu_enable),
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.alu_result (alu_result),
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.alu_result (alu_result),
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.alu_status (alu_status),
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.alu_status (alu_status),
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.alu_opcode (alu_opcode),
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.alu_opcode (alu_opcode),
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.alu_a (alu_a)
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.alu_a (alu_a)
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);
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);
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/*
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/*
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localparam period = 10;
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localparam period = 10;
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always begin
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always begin
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#(period/2) clk_i = ~clk_i;
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#(period/2) clk_i = ~clk_i;
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end
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end
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initial
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initial
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begin
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begin
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clk_i = 0;
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clk_i = 0;
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n_rst_i = 1;
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n_rst_i = 1;
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@(negedge clk_i);
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@(negedge clk_i);
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n_rst_i = 0;
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n_rst_i = 0;
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alu_opcode = LDA_IMM;
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alu_opcode = LDA_IMM;
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alu_a = 0;
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alu_a = 0;
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@(negedge clk_i);
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@(negedge clk_i);
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alu_opcode = ADC_IMM;
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alu_opcode = ADC_IMM;
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alu_a = 1;
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alu_a = 1;
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while (1) begin
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while (1) begin
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$display("op1 = %h op2 = c = %h d = %h n = %h v = %h ", alu_a, alu_status[C], alu_status[D], alu_status[N], alu_status[V]);
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$display("op1 = %h op2 = c = %h d = %h n = %h v = %h ", alu_a, alu_status[C], alu_status[D], alu_status[N], alu_status[V]);
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end
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end
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$finish;
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$finish;
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end
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end
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*/
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*/
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endmodule
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endmodule
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