library IEEE;
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_1164.all;
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use work.StimLog.all;
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use work.StimLog.all;
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entity TestBench is
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entity TestBench is
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end entity TestBench;
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end entity TestBench;
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architecture behaviour of TestBench is
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architecture behaviour of TestBench is
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signal M1_n : std_logic;
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signal M1_n : std_logic;
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signal MREQ_n : std_logic;
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signal MREQ_n : std_logic;
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signal IORQ_n : std_logic;
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signal IORQ_n : std_logic;
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signal RD_n : std_logic;
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signal RD_n : std_logic;
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signal WR_n : std_logic;
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signal WR_n : std_logic;
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signal RFSH_n : std_logic;
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signal RFSH_n : std_logic;
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signal HALT_n : std_logic;
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signal HALT_n : std_logic;
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signal WAIT_n : std_logic := '1';
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signal WAIT_n : std_logic := '1';
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signal INT_n : std_logic := '1';
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signal INT_n : std_logic := '1';
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signal NMI_n : std_logic := '1';
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signal NMI_n : std_logic := '1';
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signal RESET_n : std_logic;
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signal RESET_n : std_logic;
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signal BUSRQ_n : std_logic := '1';
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signal BUSRQ_n : std_logic := '1';
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signal BUSAK_n : std_logic;
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signal BUSAK_n : std_logic;
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signal CLK_n : std_logic := '0';
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signal CLK_n : std_logic := '0';
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signal A : std_logic_vector(15 downto 0);
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signal A : std_logic_vector(15 downto 0);
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signal D : std_logic_vector(7 downto 0);
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signal D : std_logic_vector(7 downto 0);
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signal UART_D : std_logic_vector(7 downto 0);
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signal UART_D : std_logic_vector(7 downto 0);
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signal BaudOut : std_logic;
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signal BaudOut : std_logic;
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signal TXD : std_logic;
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signal TXD : std_logic;
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signal RXD : std_logic;
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signal RXD : std_logic;
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signal CTS : std_logic := '0';
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signal CTS : std_logic := '0';
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signal DSR : std_logic := '0';
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signal DSR : std_logic := '0';
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signal RI : std_logic := '1';
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signal RI : std_logic := '1';
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signal DCD : std_logic := '0';
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signal DCD : std_logic := '0';
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signal IOWR_n : std_logic;
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signal IOWR_n : std_logic;
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signal ROMCS_n : std_logic;
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signal ROMCS_n : std_logic;
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signal RAMCS_n : std_logic;
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signal RAMCS_n : std_logic;
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signal UARTCS_n : std_logic;
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signal UARTCS_n : std_logic;
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begin
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begin
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Reset_n <= '0', '1' after 1 us;
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Reset_n <= '0', '1' after 1 us;
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-- 16 MHz clock
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-- 16 MHz clock
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CLK_n <= not CLK_n after 31.25 ns;
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CLK_n <= not CLK_n after 31.25 ns;
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IOWR_n <= WR_n or IORQ_n;
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IOWR_n <= WR_n or IORQ_n;
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ROMCS_n <= A(15) or MREQ_n;
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ROMCS_n <= A(15) or MREQ_n;
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RAMCS_n <= not A(15) or MREQ_n;
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RAMCS_n <= not A(15) or MREQ_n;
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UARTCS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
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UARTCS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
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-- NMI
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-- NMI
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NMI_n <= not D(0) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
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NMI_n <= not D(0) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
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-- INT
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-- INT
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INT_n <= not D(1) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
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INT_n <= not D(1) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
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as : AsyncStim generic map(FileName => "../../../bench/vhdl/ROM80.vhd", InterCharDelay => 100 us, Baud => 1000000, Bits => 8)
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as : AsyncStim generic map(FileName => "../../../bench/vhdl/ROM80.vhd", InterCharDelay => 100 us, Baud => 1000000, Bits => 8)
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port map(RXD);
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port map(RXD);
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al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 1000000, Bits => 8)
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al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 1000000, Bits => 8)
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port map(TXD);
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port map(TXD);
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u0 : entity work.T80a
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u0 : entity work.T80a
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port map(
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port map(
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RESET_n,
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RESET_n,
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CLK_n,
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CLK_n,
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WAIT_n,
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WAIT_n,
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INT_n,
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INT_n,
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NMI_n,
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NMI_n,
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BUSRQ_n,
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BUSRQ_n,
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M1_n,
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M1_n,
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MREQ_n,
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MREQ_n,
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IORQ_n,
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IORQ_n,
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RD_n,
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RD_n,
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WR_n,
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WR_n,
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RFSH_n,
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RFSH_n,
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HALT_n,
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HALT_n,
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BUSAK_n,
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BUSAK_n,
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A,
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A,
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D);
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D);
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u1 : entity work.ROM80
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u1 : entity work.ROM80
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port map(
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port map(
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CE_n => ROMCS_n,
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CE_n => ROMCS_n,
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OE_n => RD_n,
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OE_n => RD_n,
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A => A(14 downto 0),
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A => A(14 downto 0),
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D => D);
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D => D);
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u2 : entity work.SRAM
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u2 : entity work.SRAM
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generic map(
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generic map(
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AddrWidth => 15)
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AddrWidth => 15)
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port map(
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port map(
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CE_n => RAMCS_n,
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CE_n => RAMCS_n,
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OE_n => RD_n,
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OE_n => RD_n,
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WE_n => WR_n,
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WE_n => WR_n,
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A => A(14 downto 0),
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A => A(14 downto 0),
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D => D);
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D => D);
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D <= UART_D when UARTCS_n = '0' and RD_n = '0' else "ZZZZZZZZ";
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D <= UART_D when UARTCS_n = '0' and RD_n = '0' else "ZZZZZZZZ";
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u3 : entity work.T16450
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u3 : entity work.T16450
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port map(
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port map(
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MR_n => Reset_n,
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MR_n => Reset_n,
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XIn => CLK_n,
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XIn => CLK_n,
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RClk => BaudOut,
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RClk => BaudOut,
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CS_n => UARTCS_n,
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CS_n => UARTCS_n,
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Rd_n => RD_n,
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Rd_n => RD_n,
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Wr_n => IOWR_n,
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Wr_n => IOWR_n,
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A => A(2 downto 0),
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A => A(2 downto 0),
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D_In => D,
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D_In => D,
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D_Out => UART_D,
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D_Out => UART_D,
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SIn => RXD,
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SIn => RXD,
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CTS_n => CTS,
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CTS_n => CTS,
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DSR_n => DSR,
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DSR_n => DSR,
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RI_n => RI,
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RI_n => RI,
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DCD_n => DCD,
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DCD_n => DCD,
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SOut => TXD,
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SOut => TXD,
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RTS_n => open,
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RTS_n => open,
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DTR_n => open,
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DTR_n => open,
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OUT1_n => open,
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OUT1_n => open,
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OUT2_n => open,
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OUT2_n => open,
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BaudOut => BaudOut,
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BaudOut => BaudOut,
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Intr => open);
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Intr => open);
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end;
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end;
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