library IEEE;
|
library IEEE;
|
use IEEE.std_logic_1164.all;
|
use IEEE.std_logic_1164.all;
|
use work.StimLog.all;
|
use work.StimLog.all;
|
|
|
entity TestBench is
|
entity TestBench is
|
end entity TestBench;
|
end entity TestBench;
|
|
|
architecture behaviour of TestBench is
|
architecture behaviour of TestBench is
|
|
|
signal M1_n : std_logic;
|
signal M1_n : std_logic;
|
signal MREQ_n : std_logic;
|
signal MREQ_n : std_logic;
|
signal IORQ_n : std_logic;
|
signal IORQ_n : std_logic;
|
signal RD_n : std_logic;
|
signal RD_n : std_logic;
|
signal WR_n : std_logic;
|
signal WR_n : std_logic;
|
signal RFSH_n : std_logic;
|
signal RFSH_n : std_logic;
|
signal HALT_n : std_logic;
|
signal HALT_n : std_logic;
|
signal WAIT_n : std_logic := '1';
|
signal WAIT_n : std_logic := '1';
|
signal INT_n : std_logic := '1';
|
signal INT_n : std_logic := '1';
|
signal NMI_n : std_logic := '1';
|
signal NMI_n : std_logic := '1';
|
signal RESET_n : std_logic;
|
signal RESET_n : std_logic;
|
signal BUSRQ_n : std_logic := '1';
|
signal BUSRQ_n : std_logic := '1';
|
signal BUSAK_n : std_logic;
|
signal BUSAK_n : std_logic;
|
signal CLK_n : std_logic := '0';
|
signal CLK_n : std_logic := '0';
|
signal A : std_logic_vector(15 downto 0);
|
signal A : std_logic_vector(15 downto 0);
|
signal D : std_logic_vector(7 downto 0);
|
signal D : std_logic_vector(7 downto 0);
|
|
|
signal UART_D : std_logic_vector(7 downto 0);
|
signal UART_D : std_logic_vector(7 downto 0);
|
signal BaudOut : std_logic;
|
signal BaudOut : std_logic;
|
signal TXD : std_logic;
|
signal TXD : std_logic;
|
signal RXD : std_logic;
|
signal RXD : std_logic;
|
signal CTS : std_logic := '0';
|
signal CTS : std_logic := '0';
|
signal DSR : std_logic := '0';
|
signal DSR : std_logic := '0';
|
signal RI : std_logic := '1';
|
signal RI : std_logic := '1';
|
signal DCD : std_logic := '0';
|
signal DCD : std_logic := '0';
|
|
|
signal IOWR_n : std_logic;
|
signal IOWR_n : std_logic;
|
signal ROMCS_n : std_logic;
|
signal ROMCS_n : std_logic;
|
signal RAMCS_n : std_logic;
|
signal RAMCS_n : std_logic;
|
signal UARTCS_n : std_logic;
|
signal UARTCS_n : std_logic;
|
|
|
begin
|
begin
|
|
|
Reset_n <= '0', '1' after 1 us;
|
Reset_n <= '0', '1' after 1 us;
|
|
|
-- 16 MHz clock
|
-- 16 MHz clock
|
CLK_n <= not CLK_n after 31.25 ns;
|
CLK_n <= not CLK_n after 31.25 ns;
|
|
|
IOWR_n <= WR_n or IORQ_n;
|
IOWR_n <= WR_n or IORQ_n;
|
ROMCS_n <= A(15) or MREQ_n;
|
ROMCS_n <= A(15) or MREQ_n;
|
RAMCS_n <= not A(15) or MREQ_n;
|
RAMCS_n <= not A(15) or MREQ_n;
|
UARTCS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
|
UARTCS_n <= '0' when IORQ_n = '0' and A(7 downto 3) = "00000" else '1';
|
|
|
-- NMI
|
-- NMI
|
NMI_n <= not D(0) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
|
NMI_n <= not D(0) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
|
-- INT
|
-- INT
|
INT_n <= not D(1) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
|
INT_n <= not D(1) when IOWR_n'event and IOWR_n = '1' and A(7 downto 0) = "00001000";
|
|
|
as : AsyncStim generic map(FileName => "../../../bench/vhdl/ROM80.vhd", InterCharDelay => 100 us, Baud => 1000000, Bits => 8)
|
as : AsyncStim generic map(FileName => "../../../bench/vhdl/ROM80.vhd", InterCharDelay => 100 us, Baud => 1000000, Bits => 8)
|
port map(RXD);
|
port map(RXD);
|
|
|
al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 1000000, Bits => 8)
|
al : AsyncLog generic map(FileName => "RX_Log.txt", Baud => 1000000, Bits => 8)
|
port map(TXD);
|
port map(TXD);
|
|
|
u0 : entity work.T80a
|
u0 : entity work.T80a
|
port map(
|
port map(
|
RESET_n,
|
RESET_n,
|
CLK_n,
|
CLK_n,
|
WAIT_n,
|
WAIT_n,
|
INT_n,
|
INT_n,
|
NMI_n,
|
NMI_n,
|
BUSRQ_n,
|
BUSRQ_n,
|
M1_n,
|
M1_n,
|
MREQ_n,
|
MREQ_n,
|
IORQ_n,
|
IORQ_n,
|
RD_n,
|
RD_n,
|
WR_n,
|
WR_n,
|
RFSH_n,
|
RFSH_n,
|
HALT_n,
|
HALT_n,
|
BUSAK_n,
|
BUSAK_n,
|
A,
|
A,
|
D);
|
D);
|
|
|
u1 : entity work.ROM80
|
u1 : entity work.ROM80
|
port map(
|
port map(
|
CE_n => ROMCS_n,
|
CE_n => ROMCS_n,
|
OE_n => RD_n,
|
OE_n => RD_n,
|
A => A(14 downto 0),
|
A => A(14 downto 0),
|
D => D);
|
D => D);
|
|
|
u2 : entity work.SRAM
|
u2 : entity work.SRAM
|
generic map(
|
generic map(
|
AddrWidth => 15)
|
AddrWidth => 15)
|
port map(
|
port map(
|
CE_n => RAMCS_n,
|
CE_n => RAMCS_n,
|
OE_n => RD_n,
|
OE_n => RD_n,
|
WE_n => WR_n,
|
WE_n => WR_n,
|
A => A(14 downto 0),
|
A => A(14 downto 0),
|
D => D);
|
D => D);
|
|
|
D <= UART_D when UARTCS_n = '0' and RD_n = '0' else "ZZZZZZZZ";
|
D <= UART_D when UARTCS_n = '0' and RD_n = '0' else "ZZZZZZZZ";
|
u3 : entity work.T16450
|
u3 : entity work.T16450
|
port map(
|
port map(
|
MR_n => Reset_n,
|
MR_n => Reset_n,
|
XIn => CLK_n,
|
XIn => CLK_n,
|
RClk => BaudOut,
|
RClk => BaudOut,
|
CS_n => UARTCS_n,
|
CS_n => UARTCS_n,
|
Rd_n => RD_n,
|
Rd_n => RD_n,
|
Wr_n => IOWR_n,
|
Wr_n => IOWR_n,
|
A => A(2 downto 0),
|
A => A(2 downto 0),
|
D_In => D,
|
D_In => D,
|
D_Out => UART_D,
|
D_Out => UART_D,
|
SIn => RXD,
|
SIn => RXD,
|
CTS_n => CTS,
|
CTS_n => CTS,
|
DSR_n => DSR,
|
DSR_n => DSR,
|
RI_n => RI,
|
RI_n => RI,
|
DCD_n => DCD,
|
DCD_n => DCD,
|
SOut => TXD,
|
SOut => TXD,
|
RTS_n => open,
|
RTS_n => open,
|
DTR_n => open,
|
DTR_n => open,
|
OUT1_n => open,
|
OUT1_n => open,
|
OUT2_n => open,
|
OUT2_n => open,
|
BaudOut => BaudOut,
|
BaudOut => BaudOut,
|
Intr => open);
|
Intr => open);
|
|
|
end;
|
end;
|
|
|
