#!/usr/bin/env python
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#!/usr/bin/env python
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from distutils.core import setup
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from distutils.core import setup
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setup(name="Chips",
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setup(name="Chips",
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version="0.1.2",
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version="0.1.2",
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description="Design hardware with Python",
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description="Design hardware with Python",
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long_description="""\
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long_description="""\
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Chips
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Chips
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-----
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-----
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The Chips library allows hardware devices to be designed in python and C
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The Chips library allows hardware devices to be designed in python and C
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Features
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Features
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- Design components in C
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- Design components in C
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- Connect components together using a python API to generate a chip
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- Connect components together using a python API to generate a chip
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- Automatic generation of synthesisable Verilog.
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- Automatic generation of synthesisable Verilog.
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""",
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""",
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author="Jon Dawson",
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author="Jon Dawson",
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author_email="chips@jondawson.org.uk",
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author_email="chips@jondawson.org.uk",
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url="http://github.com/dawsonjon/Chips-2.0",
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url="http://github.com/dawsonjon/Chips-2.0",
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keywords=["Verilog", "FPGA", "C", "HDL", "Synthesis"],
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keywords=["Verilog", "FPGA", "C", "HDL", "Synthesis"],
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classifiers = [
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classifiers = [
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"Programming Language :: Python",
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"Programming Language :: Python",
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"License :: OSI Approved :: MIT License",
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"License :: OSI Approved :: MIT License",
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"Operating System :: OS Independent",
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"Operating System :: OS Independent",
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"Intended Audience :: Science/Research",
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"Intended Audience :: Science/Research",
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"Intended Audience :: Developers",
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"Intended Audience :: Developers",
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"Development Status :: 3 - Alpha",
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"Development Status :: 3 - Alpha",
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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"Topic :: Software Development :: Embedded Systems",
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"Topic :: Software Development :: Embedded Systems",
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"Topic :: Software Development :: Code Generators",
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"Topic :: Software Development :: Code Generators",
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],
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],
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packages=[
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packages=[
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"chips",
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"chips",
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"chips.compiler",
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"chips.compiler",
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"chips.api"
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"chips.api"
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],
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],
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scripts=[
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scripts=[
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"c2verilog"
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"c2verilog"
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]
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]
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)
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)
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No newline at end of file
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