#!/usr/bin/env python
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#!/usr/bin/env python
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"""compile, build and download the ATLYS demo to the ATLYS development kit"""
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"""compile, build and download the ATLYS demo to the ATLYS development kit"""
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import sys
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import sys
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import os
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import os
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import shutil
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import shutil
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from user_settings import xilinx
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from user_settings import xilinx
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current_directory = os.getcwd()
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current_directory = os.getcwd()
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working_directory = "ATLYS"
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working_directory = "ATLYS"
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shutil.copyfile("xilinx_input/ATLYS.ucf", os.path.join(working_directory, "ATLYS.ucf"))
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shutil.copyfile("xilinx_input/ATLYS.ucf", os.path.join(working_directory, "ATLYS.ucf"))
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shutil.copyfile("xilinx_input/ATLYS.prj", os.path.join(working_directory, "ATLYS.prj"))
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shutil.copyfile("xilinx_input/ATLYS.prj", os.path.join(working_directory, "ATLYS.prj"))
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shutil.copyfile("xilinx_input/xst_mixed.opt", os.path.join(working_directory, "xst_mixed.opt"))
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shutil.copyfile("xilinx_input/xst_mixed.opt", os.path.join(working_directory, "xst_mixed.opt"))
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shutil.copyfile("xilinx_input/balanced.opt", os.path.join(working_directory, "balanced.opt"))
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shutil.copyfile("xilinx_input/balanced.opt", os.path.join(working_directory, "balanced.opt"))
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shutil.copyfile("xilinx_input/bitgen.opt", os.path.join(working_directory, "bitgen.opt"))
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shutil.copyfile("xilinx_input/bitgen.opt", os.path.join(working_directory, "bitgen.opt"))
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os.chdir(working_directory)
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os.chdir(working_directory)
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if "compile" in sys.argv or "all" in sys.argv:
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if "compile" in sys.argv or "all" in sys.argv:
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print "Compiling C files using chips ...."
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print "Compiling C files using chips ...."
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retval = os.system("../chips2/c2verilog ../source/user_design_atlys.c")
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retval = os.system("../chips2/c2verilog ../source/user_design.c")
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retval = os.system("../chips2/c2verilog ../source/server.c")
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retval = os.system("../chips2/c2verilog ../source/server.c")
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if retval != 0:
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if retval != 0:
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sys.exit(-1)
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sys.exit(-1)
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if "synth_estimate" in sys.argv:
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print "Test build to estimate size ...."
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os.mkdir(os.path.join(current_directory, "synth_estimate"))
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os.chdir(os.path.join(current_directory, "synth_estimate"))
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retval = os.system("../chips2/c2verilog ../source/server.c")
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output_file = open("server.prj", "w")
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output_file.write("verilog work server.v")
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output_file.close()
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os.system("%s/xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt server"%xilinx)
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os.chdir(current_directory)
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shutil.rmtree("synth_estimate")
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if "build" in sys.argv or "all" in sys.argv:
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if "build" in sys.argv or "all" in sys.argv:
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print "Building Demo using Xilinx ise ...."
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print "Building Demo using Xilinx ise ...."
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retval = os.system("%s/xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt ATLYS"%xilinx)
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retval = os.system("%s/xflow -synth xst_mixed.opt -p XC6Slx45-CSG324 -implement balanced.opt -config bitgen.opt ATLYS"%xilinx)
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if retval != 0:
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if retval != 0:
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sys.exit(-1)
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sys.exit(-1)
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shutil.copyfile("server.v", os.path.join(current_directory, "precompiled", "server.v"))
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shutil.copyfile("ATLYS.bit", os.path.join(current_directory, "precompiled", "ATLYS.bit"))
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if "download" in sys.argv or "all" in sys.argv:
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if "download" in sys.argv or "all" in sys.argv:
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print "Downloading bit file to development kit ...."
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print "Downloading bit file to development kit ...."
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retval = os.system("sudo djtgcfg prog -d Atlys -i 0 -f ATLYS.bit")
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retval = os.system("sudo djtgcfg prog -d Atlys -i 0 -f ATLYS.bit")
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if retval != 0:
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if retval != 0:
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sys.exit(-1)
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sys.exit(-1)
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os.chdir(current_directory)
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os.chdir(current_directory)
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