-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Title : Tools Package
|
-- Title : Tools Package
|
-- Project : Utility library
|
-- Project : Utility library
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- File : tools.vhd
|
-- File : tools.vhd
|
-- Author : Jamil Khatib (khatib@ieee.org)
|
-- Author : Jamil Khatib (khatib@ieee.org)
|
-- Organization: OpenIPCore Project
|
-- Organization: OpenIPCore Project
|
-- Created : 2000/11/02
|
-- Created : 2000/11/02
|
-- Last update : 2000/11/02
|
-- Last update : 2000/11/02
|
-- Platform :
|
-- Platform :
|
-- Simulators : Modelsim 5.3XE/Windows98
|
-- Simulators : Modelsim 5.3XE/Windows98
|
-- Synthesizers:
|
-- Synthesizers:
|
-- Target :
|
-- Target :
|
-- Dependency : ieee.std_logic_1164
|
-- Dependency : ieee.std_logic_1164
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_arith
|
-- ieee.std_logic_unsigned
|
-- ieee.std_logic_unsigned
|
--
|
--
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Description: This package contains set of usefull functions and procedures
|
-- Description: This package contains set of usefull functions and procedures
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Copyright (c) 2000 Jamil Khatib
|
-- Copyright (c) 2000 Jamil Khatib
|
--
|
--
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- This VHDL design file is an open design; you can redistribute it and/or
|
-- modify it and/or implement it after contacting the author
|
-- modify it and/or implement it after contacting the author
|
-- You can check the draft license at
|
-- You can check the draft license at
|
-- http://www.opencores.org/OIPC/license.shtml
|
-- http://www.opencores.org/OIPC/license.shtml
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Revisions :
|
-- Revisions :
|
-- Revision Number : 1
|
-- Revision Number : 1
|
-- Version : 0.1
|
-- Version : 0.1
|
-- Date : 2nd Nov 2000
|
-- Date : 2nd Nov 2000
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Created
|
-- Desccription : Created
|
--
|
--
|
---------- Revisions :
|
---------- Revisions :
|
-- Revision Number : 2
|
-- Revision Number : 2
|
-- Version : 0.2
|
-- Version : 0.2
|
-- Date : 14 Nov 2000
|
-- Date : 14 Nov 2000
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Modifier : Jamil Khatib (khatib@ieee.org)
|
-- Desccription : Shift functions and int_2_slv are added
|
-- Desccription : Shift functions and int_2_slv are added
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
|
|
package tools_pkg is
|
package tools_pkg is
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- Types
|
-- Types
|
|
|
-- Memory arraye type of std_logic_vector
|
-- Memory arraye type of std_logic_vector
|
-- type std_memory_array_typ is array (integer range <>) of std_logic_vector(5 downto 0); --integer range <>);
|
-- type std_memory_array_typ is array (integer range <>) of std_logic_vector(5 downto 0); --integer range <>);
|
|
|
-- Memory arraye type of std_ulogic_vector
|
-- Memory arraye type of std_ulogic_vector
|
-- type stdu_memory_array_typ is array (integer range <>) of std_ulogic_vector(integer range <>);
|
-- type stdu_memory_array_typ is array (integer range <>) of std_ulogic_vector(integer range <>);
|
|
|
-- Sign magnitude numbers based on std_logic_vector (The msb represents the sign)
|
-- Sign magnitude numbers based on std_logic_vector (The msb represents the sign)
|
type SIGN_MAG_typ is array (natural range <>) of std_logic;
|
type SIGN_MAG_typ is array (natural range <>) of std_logic;
|
|
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
-- Functions
|
-- Functions
|
|
|
|
|
function Log2( input : integer ) return integer; -- log2 functions
|
function Log2( input : integer ) return integer; -- log2 functions
|
|
|
function slv_2_int ( SLV : std_logic_vector) return integer; --
|
function slv_2_int ( SLV : std_logic_vector) return integer; --
|
--std_logic_vector
|
--std_logic_vector
|
--to integer
|
--to integer
|
|
|
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude addition
|
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude addition
|
|
|
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude
|
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ; -- sign_magnitude
|
-- subtraction (
|
-- subtraction (
|
-- based on
|
-- based on
|
-- complement operations)
|
-- complement operations)
|
function LeftShift (
|
function LeftShift (
|
InReg : std_logic_vector; -- Input Register
|
InReg : std_logic_vector; -- Input Register
|
ShSize : std_logic_vector) -- Shift Size
|
ShSize : std_logic_vector) -- Shift Size
|
return std_logic_vector;
|
return std_logic_vector;
|
|
|
|
|
function RightShift (
|
function RightShift (
|
InReg : std_logic_vector; -- Input register
|
InReg : std_logic_vector; -- Input register
|
ShSize : std_logic_vector) -- Shift Size
|
ShSize : std_logic_vector) -- Shift Size
|
return std_logic_vector;
|
return std_logic_vector;
|
|
|
function int_2_slv (val, SIZE : integer) return std_logic_vector;
|
function int_2_slv (val, SIZE : integer) return std_logic_vector;
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
end tools_pkg;
|
end tools_pkg;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
package body tools_pkg is
|
package body tools_pkg is
|
|
|
-----------------------------------------------------------------------------
|
-----------------------------------------------------------------------------
|
function Log2(
|
function Log2(
|
input : integer ) -- input number
|
input : integer ) -- input number
|
return integer is
|
return integer is
|
variable temp, log : integer;
|
variable temp, log : integer;
|
begin
|
begin
|
|
|
assert input /= 0
|
assert input /= 0
|
report "Error : function missuse : log2(zero)"
|
report "Error : function missuse : log2(zero)"
|
severity failure;
|
severity failure;
|
temp := input;
|
temp := input;
|
log := 0;
|
log := 0;
|
while (temp /= 0) loop
|
while (temp /= 0) loop
|
temp := temp/2;
|
temp := temp/2;
|
log := log+1;
|
log := log+1;
|
end loop;
|
end loop;
|
return log;
|
return log;
|
end log2;
|
end log2;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
|
|
-- function LOG2(COUNT:INTEGER) return INTEGER is -- COUNT should be >0 variable TEMP:INTEGER;
|
-- function LOG2(COUNT:INTEGER) return INTEGER is -- COUNT should be >0 variable TEMP:INTEGER;
|
-- variable TEMP : integer;
|
-- variable TEMP : integer;
|
-- variable cnt : integer;
|
-- variable cnt : integer;
|
-- begin
|
-- begin
|
-- cnt := COUNT;
|
-- cnt := COUNT;
|
--
|
--
|
-- TEMP:=0;
|
-- TEMP:=0;
|
-- while COUNT>1 loop
|
-- while COUNT>1 loop
|
-- TEMP:=TEMP+1;
|
-- TEMP:=TEMP+1;
|
-- cnt:=cnt/2;
|
-- cnt:=cnt/2;
|
-- end loop;
|
-- end loop;
|
-- return TEMP;
|
-- return TEMP;
|
-- end log2;
|
-- end log2;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
function slv_2_int (
|
function slv_2_int (
|
SLV : std_logic_vector) -- std_logic_vector to convert
|
SLV : std_logic_vector) -- std_logic_vector to convert
|
return integer is
|
return integer is
|
|
|
variable Result : integer := 0; -- conversion result
|
variable Result : integer := 0; -- conversion result
|
|
|
begin
|
begin
|
for i in SLV'range loop
|
for i in SLV'range loop
|
Result := Result * 2; -- shift the variable to left
|
Result := Result * 2; -- shift the variable to left
|
case SLV(i) is
|
case SLV(i) is
|
when '1' | 'H' => Result := Result + 1;
|
when '1' | 'H' => Result := Result + 1;
|
when '0' | 'L' => Result := Result + 0;
|
when '0' | 'L' => Result := Result + 0;
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
end loop;
|
end loop;
|
|
|
return Result;
|
return Result;
|
end;
|
end;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
|
function "+"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
|
variable VA, VB, VR : unsigned(A'length - 1 downto 0);
|
variable VA, VB, VR : unsigned(A'length - 1 downto 0);
|
-- include the overflow bit
|
-- include the overflow bit
|
|
|
variable SA, SB, SR : std_logic;
|
variable SA, SB, SR : std_logic;
|
variable TMP, RES : SIGN_MAG_typ(A'length - 1 downto 0);
|
variable TMP, RES : SIGN_MAG_typ(A'length - 1 downto 0);
|
|
|
variable casevar : std_logic_vector(1 downto 0);
|
variable casevar : std_logic_vector(1 downto 0);
|
variable std_tmp : std_logic_vector(A'length - 1 downto 0) := (others => '0');
|
variable std_tmp : std_logic_vector(A'length - 1 downto 0) := (others => '0');
|
|
|
begin
|
begin
|
|
|
assert A'length = B'length
|
assert A'length = B'length
|
report "Error : length mismatch"
|
report "Error : length mismatch"
|
severity failure;
|
severity failure;
|
|
|
|
|
TMP := A;
|
TMP := A;
|
SA := TMP(A'length - 1);
|
SA := TMP(A'length - 1);
|
VA := '0' & unsigned(TMP(A'length - 2 downto 0));
|
VA := '0' & unsigned(TMP(A'length - 2 downto 0));
|
TMP := B;
|
TMP := B;
|
SB := TMP(B'length - 1);
|
SB := TMP(B'length - 1);
|
VB := '0' & unsigned(TMP(B'length - 2 downto 0));
|
VB := '0' & unsigned(TMP(B'length - 2 downto 0));
|
|
|
casevar := SA & SB;
|
casevar := SA & SB;
|
case casevar is
|
case casevar is
|
when "00" |"11" =>
|
when "00" |"11" =>
|
|
|
VR := VA + VB;
|
VR := VA + VB;
|
SR := SA;
|
SR := SA;
|
|
|
when "01" =>
|
when "01" =>
|
|
|
VR := VA - VB;
|
VR := VA - VB;
|
SR := VR(VR'length - 1);
|
SR := VR(VR'length - 1);
|
|
|
if SR = '1' then
|
if SR = '1' then
|
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
|
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
|
std_tmp := not std_tmp;
|
std_tmp := not std_tmp;
|
|
|
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
|
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
|
|
|
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
|
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
|
|
|
end if;
|
end if;
|
|
|
|
|
when "10" =>
|
when "10" =>
|
VR := VB - VA;
|
VR := VB - VA;
|
SR := VR(VR'length - 1);
|
SR := VR(VR'length - 1);
|
|
|
if SR = '1' then
|
if SR = '1' then
|
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
|
std_tmp(VR'length -2 downto 0) := std_logic_vector(VR(VR'length -2 downto 0));
|
std_tmp := not std_tmp;
|
std_tmp := not std_tmp;
|
|
|
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
|
VR(VR'length -2 downto 0) := unsigned(std_tmp(VR'length -2 downto 0));
|
|
|
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
|
VR(VR'length -2 downto 0) := VR(VR'length -2 downto 0) +1;
|
|
|
end if;
|
end if;
|
|
|
when others => null;
|
when others => null;
|
end case;
|
end case;
|
|
|
|
|
RES := SIGN_MAG_typ(SR & VR(VR'length -2 downto 0));
|
RES := SIGN_MAG_typ(SR & VR(VR'length -2 downto 0));
|
|
|
return RES;
|
return RES;
|
end "+";
|
end "+";
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- function "+"(A, B: SIGN_MAG) return SIGN_MAG is
|
-- function "+"(A, B: SIGN_MAG) return SIGN_MAG is
|
-- variable VA, VB, VR: UNSIGNED(A'length - 2 downto 0);
|
-- variable VA, VB, VR: UNSIGNED(A'length - 2 downto 0);
|
-- variable SA, SB, SR: STD_LOGIC;
|
-- variable SA, SB, SR: STD_LOGIC;
|
-- variable TMP, RES: SIGN_MAG(A'length - 1 downto 0);
|
-- variable TMP, RES: SIGN_MAG(A'length - 1 downto 0);
|
--begin
|
--begin
|
-- assert A'length = B'length
|
-- assert A'length = B'length
|
-- report "Error"
|
-- report "Error"
|
-- severity FAILURE;
|
-- severity FAILURE;
|
-- TMP := A;
|
-- TMP := A;
|
-- SA := TMP(A'length - 1);
|
-- SA := TMP(A'length - 1);
|
-- VA := UNSIGNED(TMP(A'length - 2 downto 0));
|
-- VA := UNSIGNED(TMP(A'length - 2 downto 0));
|
-- TMP := B;
|
-- TMP := B;
|
-- SB := TMP(B'length - 1);
|
-- SB := TMP(B'length - 1);
|
-- VB := UNSIGNED(TMP(B'length - 2 downto 0));
|
-- VB := UNSIGNED(TMP(B'length - 2 downto 0));
|
-- if (SA = SB) then
|
-- if (SA = SB) then
|
-- VR := VA + VB;
|
-- VR := VA + VB;
|
-- SR := SA;
|
-- SR := SA;
|
-- elsif (VA >= VB) then
|
-- elsif (VA >= VB) then
|
-- VR := VA - VB;
|
-- VR := VA - VB;
|
-- SR := SA;
|
-- SR := SA;
|
-- else
|
-- else
|
-- VR := VB - VA;
|
-- VR := VB - VA;
|
-- SR := SB;
|
-- SR := SB;
|
-- end if;
|
-- end if;
|
-- RES := SIGN_MAG(SR & VR);
|
-- RES := SIGN_MAG(SR & VR);
|
-- return RES;
|
-- return RES;
|
--end "+";
|
--end "+";
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
|
function "-"(A, B : SIGN_MAG_typ) return SIGN_MAG_typ is
|
variable TMP : SIGN_MAG_typ(A'length - 1 downto 0);
|
variable TMP : SIGN_MAG_typ(A'length - 1 downto 0);
|
begin
|
begin
|
assert A'length = B'length
|
assert A'length = B'length
|
report "Error : length mismach"
|
report "Error : length mismach"
|
severity failure;
|
severity failure;
|
TMP := B;
|
TMP := B;
|
TMP(B'length - 1) := not TMP(B'length - 1);
|
TMP(B'length - 1) := not TMP(B'length - 1);
|
return A + TMP;
|
return A + TMP;
|
end "-";
|
end "-";
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: combinational left shift register
|
-- purpose: combinational left shift register
|
function LeftShift (
|
function LeftShift (
|
InReg : std_logic_vector; -- Input Register
|
InReg : std_logic_vector; -- Input Register
|
ShSize : std_logic_vector) -- Shift Size
|
ShSize : std_logic_vector) -- Shift Size
|
return std_logic_vector is
|
return std_logic_vector is
|
|
|
constant REGSIZE : integer := InReg'length; -- Register Size
|
constant REGSIZE : integer := InReg'length; -- Register Size
|
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
|
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
|
-- Local storage for shifter
|
-- Local storage for shifter
|
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
|
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
|
begin
|
begin
|
|
|
VarReg := inReg;
|
VarReg := inReg;
|
|
|
for i in 0 to SHIFTSIZE -2 loop
|
for i in 0 to SHIFTSIZE -2 loop
|
|
|
|
|
if ShSize(i) = '1' then
|
if ShSize(i) = '1' then
|
|
|
VarReg(REGSIZE -1 downto 0) := VarReg( (REGSIZE-(2**i)-1) downto 0) & ((2**i)-1 downto 0 => '0');
|
VarReg(REGSIZE -1 downto 0) := VarReg( (REGSIZE-(2**i)-1) downto 0) & ((2**i)-1 downto 0 => '0');
|
|
|
end if;
|
end if;
|
|
|
end loop; -- i
|
end loop; -- i
|
|
|
if ShSize(SHIFTSIZE-1) = '1' then
|
if ShSize(SHIFTSIZE-1) = '1' then
|
VarReg := (others => '0');
|
VarReg := (others => '0');
|
end if;
|
end if;
|
|
|
return VarReg;
|
return VarReg;
|
|
|
end LeftShift;
|
end LeftShift;
|
|
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: combinational Right shift register
|
-- purpose: combinational Right shift register
|
function RightShift (
|
function RightShift (
|
InReg : std_logic_vector; -- Input register
|
InReg : std_logic_vector; -- Input register
|
ShSize : std_logic_vector) -- Shift Size
|
ShSize : std_logic_vector) -- Shift Size
|
return std_logic_vector is
|
return std_logic_vector is
|
|
|
constant REGSIZE : integer := InReg'length; -- Register Size
|
constant REGSIZE : integer := InReg'length; -- Register Size
|
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
|
variable VarReg : std_logic_vector(InReg'length -1 downto 0);
|
-- Local storage for shifter
|
-- Local storage for shifter
|
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
|
constant SHIFTSIZE : integer := log2(InReg'length); -- Shift size
|
|
|
begin -- RightShift
|
begin -- RightShift
|
|
|
|
|
|
|
|
|
VarReg := inReg;
|
VarReg := inReg;
|
|
|
for i in 0 to SHIFTSIZE -2 loop
|
for i in 0 to SHIFTSIZE -2 loop
|
|
|
|
|
if ShSize(i) = '1' then
|
if ShSize(i) = '1' then
|
|
|
VarReg(REGSIZE -1 downto 0) := (REGSIZE-1 downto REGSIZE-(2**i) => '0') & VarReg(REGSIZE -1 downto (2**i));
|
VarReg(REGSIZE -1 downto 0) := (REGSIZE-1 downto REGSIZE-(2**i) => '0') & VarReg(REGSIZE -1 downto (2**i));
|
|
|
end if;
|
end if;
|
|
|
end loop; -- i
|
end loop; -- i
|
|
|
if ShSize(SHIFTSIZE-1) = '1' then
|
if ShSize(SHIFTSIZE-1) = '1' then
|
VarReg := (others => '0');
|
VarReg := (others => '0');
|
end if;
|
end if;
|
|
|
return VarReg;
|
return VarReg;
|
|
|
|
|
end RightShift;
|
end RightShift;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
-- purpose: Integer to Std_logic_vector conversion
|
-- purpose: Integer to Std_logic_vector conversion
|
function int_2_slv (val, SIZE : integer) return std_logic_vector is
|
function int_2_slv (val, SIZE : integer) return std_logic_vector is
|
variable result : std_logic_vector(SIZE-1 downto 0);
|
variable result : std_logic_vector(SIZE-1 downto 0);
|
variable l_val : integer := val;
|
variable l_val : integer := val;
|
begin
|
begin
|
|
|
assert SIZE > 1
|
assert SIZE > 1
|
report "Error : function missuse : in_2_slv(val, negative size)"
|
report "Error : function missuse : in_2_slv(val, negative size)"
|
severity failure;
|
severity failure;
|
|
|
for i in 0 to result'length-1 loop
|
for i in 0 to result'length-1 loop
|
|
|
if (l_val mod 2) = 0 then
|
if (l_val mod 2) = 0 then
|
|
|
result(i) := '0';
|
result(i) := '0';
|
|
|
else
|
else
|
result(i) := '1';
|
result(i) := '1';
|
|
|
end if;
|
end if;
|
|
|
l_val := l_val/2;
|
l_val := l_val/2;
|
|
|
end loop;
|
end loop;
|
|
|
return result;
|
return result;
|
|
|
end int_2_slv;
|
end int_2_slv;
|
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
end tools_pkg;
|
end tools_pkg;
|
|
|
