%% $Log: not supported by cvs2svn $
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%% Revision 1.5 2001/05/25 18:43:39 jamil
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%% Revision 1.5 2001/05/25 18:43:39 jamil
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%% PreRelease reviews
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%% PreRelease reviews
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%% Revision 1.4 2001/04/10 22:24:35 jamil
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%% Revision 1.4 2001/04/10 22:24:35 jamil
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%% Wishbone logi added
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%% Wishbone logi added
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%%
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%%
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%% Revision 1.3 2001/04/09 21:33:54 jamil
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%% Revision 1.3 2001/04/09 21:33:54 jamil
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%% FIFO buffers calculations added
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%% FIFO buffers calculations added
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%%
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%% Revision 1.2 2001/04/04 21:28:56 jamil
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%% Revision 1.2 2001/04/04 21:28:56 jamil
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%% ISDN support added
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%% ISDN support added
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%%
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%%
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\documentclass[a4paper,11pt]{article}
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\author{Jamil Khatib}
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\author{Jamil Khatib}
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\title{TDM controller core}
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\title{TDM controller core}
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%% Hyphenation list %%
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%% Hyphenation list %%
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\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}
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\hyphenation{OpenIP OpenIPCore OpenHW OpenDesign OpenCores ISP CPLD FPGA CAD VHDL hard-ware soft-ware DSP ASIC}
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%%Headers & footers
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\lhead{\uppercase\rightmark}
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\chead{}
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\chead{}
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\rhead{\bfseries \opencores Project}
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\rhead{\bfseries \opencores Project}
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\lfoot{TDM controller}
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\lfoot{TDM controller}
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\cfoot{}
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%% begin Document
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\begin{document}
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\begin{document}
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%% Cover page
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%% Cover page
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\maketitle
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\maketitle
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\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}
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\begin{center}(C) Copyright 2001 Jamil Khatib.\end{center}
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\tableofcontents
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\tableofcontents
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\newpage
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\newpage
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\section{List of authors and changes}
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\section{List of authors and changes}
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\begin{tabular}{|l|l|l|l|l|}
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\begin{tabular}{|l|l|l|l|l|}
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\hline
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\hline
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Name & Changes & Date & Contact address\\
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Name & Changes & Date & Contact address\\
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\hline
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\hline
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\hline
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\hline
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\addauthor{Jamil Khatib}{Initial release}{3-2-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{Initial release}{3-2-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{General review and CPU interface added}{10-2-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{General review and CPU interface added}{10-2-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{ISDN support added}{3-4-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{ISDN support added}{3-4-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{Buffer Calculations added}{9-4-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{Buffer Calculations added}{9-4-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{General review}{25-5-2001}{khatib@ieee.org}
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\addauthor{Jamil Khatib}{General review}{25-5-2001}{khatib@ieee.org}
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\newpage
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%%------------------------------------------%%
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%%------------------------------------------%%
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\section{Project Definition}
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\section{Project Definition}
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\subsection{Introduction}
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\subsection{Introduction}
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Time devision multiplexing is a scheme used to communicate between systems or devices via shared interface lines. Each device or system gets the access to this interface in a single time slot.
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Time devision multiplexing is a scheme used to communicate between systems or devices via shared interface lines. Each device or system gets the access to this interface in a single time slot.
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\subsection{Objectives}
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\subsection{Objectives}
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The aim of this project is to develop the basic TDM functionalities to be used by many communication systems like ISDN, E1, and voice codecs.
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The aim of this project is to develop the basic TDM functionalities to be used by many communication systems like ISDN, E1, and voice codecs.
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%%- New section -%%
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%%- New section -%%
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%%------------------------------------------%%
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%%------------------------------------------%%
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\section{Specifications}
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\section{Specifications}
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\subsection{System Features Specification}
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\subsection{System Features Specification}
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\begin{enumerate}
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\begin{enumerate}
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\item Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps)
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\item Supports E1 bit rate and time slots (32 time slots or 32 DS0 channels at bit rate 2.048Mbps)
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\item Supports ST-Bus (Serial Telecom bus) interface.
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\item Supports ST-Bus (Serial Telecom bus) interface.
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\item Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.
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\item Routes time slots to/from HDLC controller via the backend interface and software support or to/from memory.
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\item Supports read for all or partial TDM slots from the ST-bus.
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\item Supports read for all or partial TDM slots from the ST-bus.
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\item Supports write for all or partial TDM slots to ST-bus.
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\item Supports write for all or partial TDM slots to ST-bus.
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\item It supports $N\times 64$ mode (i.e. it supports sampling (or writing) to $N$ consecutive time slots)
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\item It supports $N\times 64$ mode (i.e. it supports sampling (or writing) to $N$ consecutive time slots)
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\item Supports two serial lines one input and one output.
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\item Supports two serial lines one input and one output.
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\item Can be connected to other ST-Bus compatible devices via serial or star configurations.
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\item Can be connected to other ST-Bus compatible devices via serial or star configurations.
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\item If no data is available for transmission it sends all ones.
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\item If no data is available for transmission it sends all ones.
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\item Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
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\item Backend interface uses the Wishbone bus interface which can be connected directly to the system or via FIFO buffer.
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\item Optional External FIFO buffer, configuration and status registers.
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\item Optional External FIFO buffer, configuration and status registers.
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\item The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel.
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\item The core will be made of two levels of hierarchies, the basic functionality and the Optional interfaces and buffers which makes it easy to add extra serial lines by duplicating the TDM controllers in parallel.
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\item ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots.
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\item ISDN (2B+D) support can be supported by adding three parallel HDLC controllers on the first three time slots.
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%\item Shared memory interface will be added in the future instead of the internal FIFOs for systems that support shared memory.
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%\item Shared memory interface will be added in the future instead of the internal FIFOs for systems that support shared memory.
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\end{enumerate}
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\end{enumerate}
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\subsection{External Interfaces}
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\subsection{External Interfaces}
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\begin{tabular}{|l|l|l|}
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\begin{tabular}{|l|l|l|}
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\hline
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\hline
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Signal name& Direction& Description\\
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Signal name& Direction& Description\\
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\hline
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\hline
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\hline
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\hline
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Control interface & & \\
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Control interface & & \\
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\hline
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\hline
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\hline
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\hline
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CLK\_I & Input & System clock \\
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CLK\_I & Input & System clock \\
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Rst\_n & Input & System asynchronous reset (active low)\\
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Rst\_n & Input & System asynchronous reset (active low)\\
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NoChannels[4:0] & Input & Number of time slots (Can be fixed)\\
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NoChannels[4:0] & Input & Number of time slots (Can be fixed)\\
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DropChannels[4:0] & Input & Number of time slots to be dropped (Can be fixed)\\
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DropChannels[4:0] & Input & Number of time slots to be dropped (Can be fixed)\\
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\hline
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\hline
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\hline
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\hline
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Serial Interface (ST-Bus)& & \\
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Serial Interface (ST-Bus)& & \\
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\hline
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\hline
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\hline
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\hline
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C2 & Input & Bus Clock\\
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C2 & Input & Bus Clock\\
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DSTi & Input& Receive serial Data\\
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DSTi & Input& Receive serial Data\\
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DSTo & Output & Transmit serial Data\\
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DSTo & Output & Transmit serial Data\\
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F0\_n & Input & Framing pulse (active low)\\
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F0\_n & Input & Framing pulse (active low)\\
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F0od\_n & Output & Delayed Framing pulse (active low) generated after the channels has handled\\
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F0od\_n & Output & Delayed Framing pulse (active low) generated after the channels has handled\\
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\hline
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\hline
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\hline
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\hline
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Back-end Interface (Received)& &\\
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Back-end Interface (Received)& &\\
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\hline
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\hline
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\hline
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\hline
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RxD[7:0]& Output& Receive data bus\\
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RxD[7:0]& Output& Receive data bus\\
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RxValidData& Output& Valid Data\\
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RxValidData& Output& Valid Data\\
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FrameErr& Output& Error in the received data\\
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FrameErr& Output& Error in the received data\\
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Read& Input& Read byte\\
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Read& Input& Read byte\\
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Ready& Output& Valid data exists\\
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Ready& Output& Valid data exists\\
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\hline
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\hline
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\hline
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\hline
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Back-end Interface (Transmited)& &\\
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Back-end Interface (Transmited)& &\\
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\hline
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\hline
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\hline
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\hline
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TxD[7:0]& Input& Transmit data bus\\
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TxD[7:0]& Input& Transmit data bus\\
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TxValidData& Input& Valid Data\\
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TxValidData& Input& Valid Data\\
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Write& Input& Write byte\\
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Write& Input& Write byte\\
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Ready& Output& Ready to get data\\
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Ready& Output& Ready to get data\\
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TxErr& Output& Buffer under flow\\
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TxErr& Output& Buffer under flow\\
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\hline
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\hline
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\end{tabular}
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\end{tabular}
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\subsubsection{Back-end interface mapping to Wishbone SoC bus}
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\subsubsection{Back-end interface mapping to Wishbone SoC bus}
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The TDM backend interface is divided into two parts one for receive and one for transmit.It can be used as a slave core or master according to the below mapping. The core supports SINGLE READ/WRITE Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
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The TDM backend interface is divided into two parts one for receive and one for transmit.It can be used as a slave core or master according to the below mapping. The core supports SINGLE READ/WRITE Cycle only using 8-bit data bus without address lines. The choice between master and slave is left for the system integrator and must do the configuration and glue logic as defined in the tables.
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\\
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\\
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\begin{figure}[!h]
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\begin{figure}[!h]
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\includegraphics[angle=0,width=\textwidth,scale=.5]{wishlogo.ps}
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\includegraphics[angle=0,width=\textwidth,scale=.5]{wishlogo.ps}
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\label{Logo}
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\label{Logo}
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\end{figure}
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\end{figure}
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\begin{tabular}{|l|l|}
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\begin{tabular}{|l|l|}
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\hline
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\hline
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Signal Name& Wishbone signal\\
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Signal Name& Wishbone signal\\
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\hline
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\hline
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\hline
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\hline
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Master Configuration connected to FIFO& Receive channel\\
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Master Configuration connected to FIFO& Receive channel\\
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\hline
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\hline
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CLK\_I & CLK\_I\\
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CLK\_I & CLK\_I\\
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Rst & not RST\_I\\
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Rst & not RST\_I\\
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RxD[7:0]& DAT\_O(7:0)\\
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RxD[7:0]& DAT\_O(7:0)\\
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RxValidData& STB\_O\\
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RxValidData& STB\_O\\
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RxValidData& CYC\_O\\
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RxValidData& CYC\_O\\
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Read& ACK\_I and not RTY\_I\\
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Read& ACK\_I and not RTY\_I\\
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Ready& WE\_O\\
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Ready& WE\_O\\
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FrameERR& TAG0\_O\\
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FrameERR& TAG0\_O\\
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\hline
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\hline
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Slave FIFO(two-clock domain FIFO)&\\
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Slave FIFO(two-clock domain FIFO)&\\
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\hline
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\hline
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Data[7:0]& DAT\_I(7:0)\\
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Data[7:0]& DAT\_I(7:0)\\
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Chip Select& STB\_I\\
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Chip Select& STB\_I\\
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STB\_I and not FullFlag& ACK\_O\\
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STB\_I and not FullFlag& ACK\_O\\
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FullFlag& RTY\_O\\
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FullFlag& RTY\_O\\
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Write& WE\_I\\
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Write& WE\_I\\
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\hline
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\hline
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Slave Configuration &\\
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Slave Configuration &\\
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\hline
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\hline
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CLK\_I & CLK\_I\\
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CLK\_I & CLK\_I\\
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Rst & not RST\_I\\
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Rst & not RST\_I\\
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RxD[7:0]& DAT\_O(7:0)\\
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RxD[7:0]& DAT\_O(7:0)\\
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RxValidData& TAG0\_O\\
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RxValidData& TAG0\_O\\
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ReadByte& not WE\_I\\
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ReadByte& not WE\_I\\
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Ready& not RTY\_O\\
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Ready& not RTY\_O\\
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STB\_I and not WR\_I& ACK\_O\\
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STB\_I and not WR\_I& ACK\_O\\
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FrameERR& TAG1\_O\\
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FrameERR& TAG1\_O\\
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\hline
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\hline
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\end{tabular}
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\end{tabular}
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%%%%%%%%%%%%
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%%%%%%%%%%%%
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\begin{tabular}{|l|l|}
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\begin{tabular}{|l|l|}
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\hline
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\hline
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Signal Name& Wishbone signal\\
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Signal Name& Wishbone signal\\
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\hline
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\hline
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\hline
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\hline
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Master Configuration connected to FIFO& Transmit channel\\
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Master Configuration connected to FIFO& Transmit channel\\
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\hline
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\hline
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\hline
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\hline
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C2 & CLK\_I\\
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C2 & CLK\_I\\
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Rst & not RST\_I\\
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Rst & not RST\_I\\
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TxD[7:0]& DAT\_I(7:0)\\
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TxD[7:0]& DAT\_I(7:0)\\
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Write& ACK\_I and not RTY\_I\\
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Write& ACK\_I and not RTY\_I\\
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Ready& not WE\_O\\
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Ready& not WE\_O\\
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TxValidData& TAG0\_I\\
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TxValidData& TAG0\_I\\
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Always Active & CYC\_O\\
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Always Active & CYC\_O\\
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Always Active & STB\_O\\
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Always Active & STB\_O\\
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\hline
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\hline
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Slave FIFO(two-clock domain FIFO)&\\
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Slave FIFO(two-clock domain FIFO)&\\
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\hline
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\hline
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Data[31:0]& DAT\_I(31:0)\\
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Data[31:0]& DAT\_I(31:0)\\
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EmptyFlag& RTY\_O\\
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EmptyFlag& RTY\_O\\
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Read& WE\_I\\
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Read& WE\_I\\
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WE\_I and not EmptyFlag& ACK\_O\\
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WE\_I and not EmptyFlag& ACK\_O\\
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ChipSelect& STB\_I\\
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ChipSelect& STB\_I\\
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\hline
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\hline
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Slave Configuration &\\
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Slave Configuration &\\
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\hline
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\hline
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C2 & CLK\_I\\
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C2 & CLK\_I\\
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Rst & not RST\_I\\
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Rst & not RST\_I\\
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TxD[7:0]& DAT\_I(7:0)\\
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TxD[7:0]& DAT\_I(7:0)\\
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TxValidData& STB\_I\\
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TxValidData& STB\_I\\
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Write& WE\_I\\
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Write& WE\_I\\
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Ready& not RTY\_O\\
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Ready& not RTY\_O\\
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STB\_I and WR\_I& ACK\_O\\
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STB\_I and WR\_I& ACK\_O\\
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\hline
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\hline
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|
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\end{tabular}
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\end{tabular}
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\subsubsection{CPU interface}
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\subsubsection{CPU interface}
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This interface is used when the FIFO and registers are included in the Core. This interface is compatible to WishBone slave bus interface that supports single read/write cycles and block cycles. The interface supports the following wishbone signals.
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This interface is used when the FIFO and registers are included in the Core. This interface is compatible to WishBone slave bus interface that supports single read/write cycles and block cycles. The interface supports the following wishbone signals.
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\begin{tabular}{|l|l|}
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\begin{tabular}{|l|l|}
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\hline
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\hline
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Signal& Note\\
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Signal& Note\\
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\hline
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\hline
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\hline
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\hline
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RST\_I& Reset\\
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RST\_I& Reset\\
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CLK\_I& Clock\\
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CLK\_I& Clock\\
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ADR\_I(2:0)& 3-bit address line\\
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ADR\_I(2:0)& 3-bit address line\\
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DAT\_O(7:0)& 8-bit receive data\\
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DAT\_O(7:0)& 8-bit receive data\\
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DAT\_I(7:0)& 8-bit transmit data\\
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DAT\_I(7:0)& 8-bit transmit data\\
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WE\_I& Read/write\\
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WE\_I& Read/write\\
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STB\_I& Strobe\\
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STB\_I& Strobe\\
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ACK\_O& Acknowledge\\
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ACK\_O& Acknowledge\\
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CYC\_I& Cycle\\
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CYC\_I& Cycle\\
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RTY\_O& Retry\\
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RTY\_O& Retry\\
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TAG0\_O& TxDone interrupt\\
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TAG0\_O& TxDone interrupt\\
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TAG1\_O& RxReady interrupt\\
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TAG1\_O& RxReady interrupt\\
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\hline
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\hline
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\end{tabular}
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\end{tabular}
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%%- New section -%%
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%%- New section -%%
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%%------------------------------------------%%
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%%------------------------------------------%%
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\section{Internal Blocks}
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\section{Internal Blocks}
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%%- New section -%%
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%%- New section -%%
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%%------------------------------------------%%
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%%------------------------------------------%%
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\section{Design description}
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\section{Design description}
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\subsection{ST-Bus interface}
|
\subsection{ST-Bus interface}
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The TDM controller interfaces to the TDM lines via serial telecom bus. The interface uses the external input clock (2.048MHz) for all of the internal serial logic. It detects the incoming framing pulse to synchronize the sampling and transmission of bits. The core reads and writes only the specified number of TDM channels (8-bits) by the size bus (No. of channels register). In the transmission mode the output pin should be disabled after writing the configured time slots. It generates also the output delayed framing pulse after it samples all the specified bits (TDM channels). This feature can be used to cascade controllers for different TDM channels.
|
The TDM controller interfaces to the TDM lines via serial telecom bus. The interface uses the external input clock (2.048MHz) for all of the internal serial logic. It detects the incoming framing pulse to synchronize the sampling and transmission of bits. The core reads and writes only the specified number of TDM channels (8-bits) by the size bus (No. of channels register). In the transmission mode the output pin should be disabled after writing the configured time slots. It generates also the output delayed framing pulse after it samples all the specified bits (TDM channels). This feature can be used to cascade controllers for different TDM channels.
|
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\subsubsection{Design notes}
|
\subsubsection{Design notes}
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\subsubsection{Timing}
|
\subsubsection{Timing}
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\subsection{External FIFO}
|
\subsection{External FIFO}
|
The controller has optional external FIFO buffers, one for data to be transmitted and one for data to be received. Status and control registers are available to control these FIFOs. These two blocks (FIFOs and registers) are built around the TDM controller core which make them optional if the core is to be used in different kind of applications.
|
The controller has optional external FIFO buffers, one for data to be transmitted and one for data to be received. Status and control registers are available to control these FIFOs. These two blocks (FIFOs and registers) are built around the TDM controller core which make them optional if the core is to be used in different kind of applications.
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|
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The current implementation supports the following configuration:
|
The current implementation supports the following configuration:
|
The size of the Transmit and receive FIFOs is $(8\times 32)$ bits which enables the whole TDM frame to be buffered.
|
The size of the Transmit and receive FIFOs is $(8\times 32)$ bits which enables the whole TDM frame to be buffered.
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|
The transmit buffer is used to prevent underflow while transmitting bytes to the line. All bytes will be available once the transmit is enabled. If the transmit FIFO is empty the core will transmit ones. The Receive buffer is used to provide data burst transfer to the Back end interface which prevents the back end from reading each byte alone. The FIFO size is suitable for operating frequencies 2.048MHz on the serial interface and 20 MHz on the back end interface. Other frequencies can operate if the back end can read the entire TDM frame before the first byte of the next frame is written (the next calculations is an example to be applied for different frequencies)
|
The transmit buffer is used to prevent underflow while transmitting bytes to the line. All bytes will be available once the transmit is enabled. If the transmit FIFO is empty the core will transmit ones. The Receive buffer is used to provide data burst transfer to the Back end interface which prevents the back end from reading each byte alone. The FIFO size is suitable for operating frequencies 2.048MHz on the serial interface and 20 MHz on the back end interface. Other frequencies can operate if the back end can read the entire TDM frame before the first byte of the next frame is written (the next calculations is an example to be applied for different frequencies)
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8 bits (Time needed to receive the first byte of the next frame) / 2.048MHz = 3.9 us
|
8 bits (Time needed to receive the first byte of the next frame) / 2.048MHz = 3.9 us
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|
|
32 Bytes (Maximum frame size) / 20MHz = 1.6 us
|
32 Bytes (Maximum frame size) / 20MHz = 1.6 us
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These FIFOs are implemented on Single port memory. It is the responsibility of the external interface to write/read data to/from the FIFOs. TxDone and RxRdy interrupts are generated when the Tx buffer is empty and Rx buffer has data respectively .
|
These FIFOs are implemented on Single port memory. It is the responsibility of the external interface to write/read data to/from the FIFOs. TxDone and RxRdy interrupts are generated when the Tx buffer is empty and Rx buffer has data respectively .
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\subsubsection{Notes}
|
\subsubsection{Notes}
|
\begin{itemize}
|
\begin{itemize}
|
%%\item \textbf{Transmit Operation:} The transmit FIFO interface uses RTY\_O signal when the FIFO is full which means that the core can not accept more data. The writing to the Transmit FIFO register can be retried when the RTY\_O signal is deasserted on the same cycle or on new burst cycle.
|
%%\item \textbf{Transmit Operation:} The transmit FIFO interface uses RTY\_O signal when the FIFO is full which means that the core can not accept more data. The writing to the Transmit FIFO register can be retried when the RTY\_O signal is deasserted on the same cycle or on new burst cycle.
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\item \textbf{Transmit Operation:} If the transmit FIFO is empty not enough data bytes is available according to no. of channels (caused by incomplete burst transfer}, the core sets the Aborted bit in the TX status and control register and sends all ones in the transmit serial line.
|
\item \textbf{Transmit Operation:} If the transmit FIFO is empty not enough data bytes is available according to no. of channels (caused by incomplete burst transfer}, the core sets the Aborted bit in the TX status and control register and sends all ones in the transmit serial line.
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|
\item \textbf{Transmit Operation:} The back end (software) should write data to the Tx buffer register according to the configured number of time slots. The transmission will start only after the specified number of slots are available in the buffer other wise Aborted bit of the Tx Status register will be set and all ones will be transmitted in this slot.
|
\item \textbf{Transmit Operation:} The back end (software) should write data to the Tx buffer register according to the configured number of time slots. The transmission will start only after the specified number of slots are available in the buffer other wise Aborted bit of the Tx Status register will be set and all ones will be transmitted in this slot.
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\item \textbf{Receive Operation:} When Receive FIFO is full It drops the second FIFO contents and sets overflow bit in the Rx Status and Control register.
|
\item \textbf{Receive Operation:} When Receive FIFO is full It drops the second FIFO contents and sets overflow bit in the Rx Status and Control register.
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|
|
\item \textbf{Receive Operation:} When RxRdy Interrupt is asserted (or RxRdy bit is set) the back end interface (software) must read the specified number of slots from the Rx Data buffer register or the buffer will not be marked as empty.
|
\item \textbf{Receive Operation:} When RxRdy Interrupt is asserted (or RxRdy bit is set) the back end interface (software) must read the specified number of slots from the Rx Data buffer register or the buffer will not be marked as empty.
|
%\item \textbf{Receive Operation:} When the FIFO is empty the core uses the RTY\_O signal to indicate no more read can be done from the Rx FIFO register.
|
%\item \textbf{Receive Operation:} When the FIFO is empty the core uses the RTY\_O signal to indicate no more read can be done from the Rx FIFO register.
|
\end{itemize}
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\end{itemize}
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|
|
\subsection{ISDN support}
|
\subsection{ISDN support}
|
In order to provide $(2B+D)$ ISDN support three HDLC controllers should be used on three time slots. The serial data the of first three time slots will enter (or get out) directly to (from) the three parallel HDLC controllers if HDLCen bit is set in the Tx Status and Control register. The HDLC controllers will be managed through the enable signals (each controller will be enabled on its corresponding time slot).
|
In order to provide $(2B+D)$ ISDN support three HDLC controllers should be used on three time slots. The serial data the of first three time slots will enter (or get out) directly to (from) the three parallel HDLC controllers if HDLCen bit is set in the Tx Status and Control register. The HDLC controllers will be managed through the enable signals (each controller will be enabled on its corresponding time slot).
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|
Eventhoush the ISDN controller is based on TDM but separate controller will be used that extracts and writes 2B+D only.
|
Eventhoush the ISDN controller is based on TDM but separate controller will be used that extracts and writes 2B+D only.
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\begin{figure}[!h]
|
\begin{figure}[!h]
|
\includegraphics[angle=0,width=\textwidth]{tdm_ISDN_top.ps}
|
\includegraphics[angle=0,width=\textwidth]{tdm_ISDN_top.ps}
|
\caption{ISDN support}\label{isdn}
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\caption{ISDN support}\label{isdn}
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\end{figure}
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\end{figure}
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\subsection{Registers}
|
\subsection{Registers}
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All internal registers are 32-bit width.
|
All internal registers are 32-bit width.
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|
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\subsubsection{Transmit}
|
\subsubsection{Transmit}
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\begin{tabular}{l l}
|
\begin{tabular}{l l}
|
\textbf{Tx Status and Control Register: Tx\_SC} & Offset Address = 0x0\\
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\textbf{Tx Status and Control Register: Tx\_SC} & Offset Address = 0x0\\
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\end{tabular}\\
|
\end{tabular}\\
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|
|
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
|
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
|
\hline
|
\hline
|
\hline
|
\hline
|
BIT & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
|
BIT & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
|
\hline
|
\hline
|
FIELD &N/A &N/A &N/A & N/A& must be set to 0& TxUnderflow& TxOverflow& TxDone(empty)\\
|
FIELD &N/A &N/A &N/A & N/A& must be set to 0& TxUnderflow& TxOverflow& TxDone(empty)\\
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\hline
|
\hline
|
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
|
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
|
\hline
|
\hline
|
R/W & RO& RO& RO& RO& RW& RO& RO& RO\\
|
R/W & RO& RO& RO& RO& RW& RO& RO& RO\\
|
\hline
|
\hline
|
\end{tabular}\\
|
\end{tabular}\\
|
|
|
\begin{tabular}{l l}
|
\begin{tabular}{l l}
|
\textbf{Tx FIFO buffer register: Tx\_Buffer} & Offset Address = 0x1\\
|
\textbf{Tx FIFO buffer register: Tx\_Buffer} & Offset Address = 0x1\\
|
\end{tabular}\\
|
\end{tabular}\\
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|
\begin{tabular}{|l||c|}
|
\begin{tabular}{|l||c|}
|
\hline
|
\hline
|
\hline
|
\hline
|
BIT & 31-0\\
|
BIT & 31-0\\
|
\hline
|
\hline
|
FIELD & Transmit Data\\
|
FIELD & Transmit Data\\
|
\hline
|
\hline
|
RESET & 0x0\\
|
RESET & 0x0\\
|
\hline
|
\hline
|
R/W & WO\\
|
R/W & WO\\
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
writing before TxDone is set has no effect. Extra writes more than defined by noChannels - DropChannels has no effect either.
|
writing before TxDone is set has no effect. Extra writes more than defined by noChannels - DropChannels has no effect either.
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|
|
\subsubsection{Receive}
|
\subsubsection{Receive}
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|
|
\begin{tabular}{l l}
|
\begin{tabular}{l l}
|
\textbf{Rx Status and Control Register: Rx\_SC} & Offset Address = 0x2\\
|
\textbf{Rx Status and Control Register: Rx\_SC} & Offset Address = 0x2\\
|
\end{tabular}\\
|
\end{tabular}\\
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|
|
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
|
\begin{tabular}{|l||c|c|c|c|c|c|c|c|}
|
\hline
|
\hline
|
\hline
|
\hline
|
BIT & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
|
BIT & 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
|
\hline
|
\hline
|
FIELD &N/A &N/A &N/A & N/A& N/A& RxBufferOverflow& RxLineOverflow& RxReady(Full)\\
|
FIELD &N/A &N/A &N/A & N/A& N/A& RxBufferOverflow& RxLineOverflow& RxReady(Full)\\
|
\hline
|
\hline
|
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
|
RESET & 0& 0& 0& 0& 0& 0& 0& 0\\
|
\hline
|
\hline
|
R/W & RO& RO& RO& RO& RO& RO& RO& RO\\
|
R/W & RO& RO& RO& RO& RO& RO& RO& RO\\
|
\hline
|
\hline
|
\end{tabular}\\
|
\end{tabular}\\
|
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|
RxLineOverflow: Overflow on serial Line buffer.
|
RxLineOverflow: Overflow on serial Line buffer.
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|
|
\begin{tabular}{l l}
|
\begin{tabular}{l l}
|
\textbf{Rx FIFO buffer register: Rx\_Buffer} & Offset Address = 0x3\\
|
\textbf{Rx FIFO buffer register: Rx\_Buffer} & Offset Address = 0x3\\
|
\end{tabular}\\
|
\end{tabular}\\
|
|
|
\begin{tabular}{|l||c|}
|
\begin{tabular}{|l||c|}
|
\hline
|
\hline
|
\hline
|
\hline
|
BIT & 31-0\\
|
BIT & 31-0\\
|
\hline
|
\hline
|
FIELD & Received Data byte\\
|
FIELD & Received Data byte\\
|
\hline
|
\hline
|
RESET & 0x0\\
|
RESET & 0x0\\
|
\hline
|
\hline
|
R/W & RO\\
|
R/W & RO\\
|
\hline
|
\hline
|
\end{tabular}\\
|
\end{tabular}\\
|
Reading before RxRdy is set or more than NoChannels-DropChannels carries no data.
|
Reading before RxRdy is set or more than NoChannels-DropChannels carries no data.
|
|
|
\begin{tabular}{l l}
|
\begin{tabular}{l l}
|
\textbf{configuration register: CFG} & Offset Address = 0x4\\
|
\textbf{configuration register: CFG} & Offset Address = 0x4\\
|
\end{tabular}\\
|
\end{tabular}\\
|
|
|
\begin{tabular}{|l||c|c|c|}
|
\begin{tabular}{|l||c|c|c|}
|
\hline
|
\hline
|
\hline
|
\hline
|
BIT & 12-8 &7-5 &4-0\\
|
BIT & 12-8 &7-5 &4-0\\
|
\hline
|
\hline
|
FIELD & DropChannels & reserved & No. of channels\\
|
FIELD & DropChannels & reserved & No. of channels\\
|
\hline
|
\hline
|
RESET & 0x00 & 0X0 &0x00\\
|
RESET & 0x00 & 0X0 &0x00\\
|
\hline
|
\hline
|
R/W & RW& RO & RW\\
|
R/W & RW& RO & RW\\
|
\hline
|
\hline
|
\end{tabular}\\
|
\end{tabular}\\
|
No of channels indicates total number of channels to be handled after the framing pulse by the controller. Single channel at least must be handled so 0x00 indicates single channel and so on.\\
|
No of channels indicates total number of channels to be handled after the framing pulse by the controller. Single channel at least must be handled so 0x00 indicates single channel and so on.\\
|
DropChannels indicates number of channels to be dropped (not handled) after the framing pulse and before the first channel to be handled.\\
|
DropChannels indicates number of channels to be dropped (not handled) after the framing pulse and before the first channel to be handled.\\
|
|
|
Example number of channels to be read is 2 starting after 3 channels from the framing pulse: $NoChannels = 0x04$ and $DropChannels = 0x03$\\
|
Example number of channels to be read is 2 starting after 3 channels from the framing pulse: $NoChannels = 0x04$ and $DropChannels = 0x03$\\
|
|
|
|
|
\textbf{ISDN registers} The ISDN controller is a separate core that has three HDLC controllers. Each HDLC controller has its own Wishbone interface and registers for information about the HDLC registers refer to the HDLC core document.
|
\textbf{ISDN registers} The ISDN controller is a separate core that has three HDLC controllers. Each HDLC controller has its own Wishbone interface and registers for information about the HDLC registers refer to the HDLC core document.
|
|
|
|
|
|
|
\subsection{Diagrams}
|
\subsection{Diagrams}
|
|
|
\begin{figure}[!h]
|
\begin{figure}[!h]
|
\includegraphics[angle=0,width=\textwidth]{tdm_core.ps}
|
\includegraphics[angle=0,width=\textwidth]{tdm_core.ps}
|
\caption{TDM core}\label{Core}
|
\caption{TDM core}\label{Core}
|
\end{figure}
|
\end{figure}
|
|
|
|
|
\begin{figure}[!h]
|
\begin{figure}[!h]
|
\includegraphics[angle=0,width=\textwidth]{tdm_top.ps}
|
\includegraphics[angle=0,width=\textwidth]{tdm_top.ps}
|
\caption{TDM controller}\label{top}
|
\caption{TDM controller}\label{top}
|
\end{figure}
|
\end{figure}
|
|
|
%%- New section -%%
|
%%- New section -%%
|
%%------------------------------------------%%
|
%%------------------------------------------%%
|
\section{Testing and verifications}
|
\section{Testing and verifications}
|
|
|
|
|
\begin{tabular}{|l|l|l|}
|
\begin{tabular}{|l|l|l|}
|
\hline
|
\hline
|
Requirement & Test method & Validation method \\
|
Requirement & Test method & Validation method \\
|
\hline
|
\hline
|
\hline
|
\hline
|
Interface timing & &\\
|
Interface timing & &\\
|
\hline
|
\hline
|
& & \\
|
& & \\
|
\hline
|
\hline
|
\hline
|
\hline
|
Functionality & & \\
|
Functionality & & \\
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
\subsection{Simulation and Test benches}
|
\subsection{Simulation and Test benches}
|
|
|
\subsection{Verification techniques and algorithms}
|
\subsection{Verification techniques and algorithms}
|
|
|
\subsection{Test plans}
|
\subsection{Test plans}
|
|
|
%%- New section -%%
|
%%- New section -%%
|
%%------------------------------------------%%
|
%%------------------------------------------%%
|
\section{Implementations}
|
\section{Implementations}
|
|
|
The design is implemented using the VHDL language. The design is divided into three blocks, serial interface, Buffers and Wishbone interface with internal registers. The TDM controller uses the wishbone clock as its main clock and uses the ST-bus clock as enables for the internal logic.
|
The design is implemented using the VHDL language. The design is divided into three blocks, serial interface, Buffers and Wishbone interface with internal registers. The TDM controller uses the wishbone clock as its main clock and uses the ST-bus clock as enables for the internal logic.
|
|
|
|
|
\subsection{Scripts, files and any other information}
|
\subsection{Scripts, files and any other information}
|
\begin{tabular}{|l|l|}
|
\begin{tabular}{|l|l|}
|
\hline
|
\hline
|
Core Files & \\
|
Core Files & \\
|
\hline
|
\hline
|
tdm\_cont.vhd & Serial Interface\\
|
tdm\_cont.vhd & Serial Interface\\
|
RxTDMBuff.vhd & Rx Buffer\\
|
RxTDMBuff.vhd & Rx Buffer\\
|
TxTDMBuffer.vhd & Tx Buffer\\
|
TxTDMBuffer.vhd & Tx Buffer\\
|
tdm\_wb\_if.vhd & Wish bone interface and registers\\
|
tdm\_wb\_if.vhd & Wish bone interface and registers\\
|
tdm\_core\_top.vhd & TDM top block\\
|
tdm\_core\_top.vhd & TDM top block\\
|
components\_pkg.vhd & TDM core components\\
|
components\_pkg.vhd & TDM core components\\
|
\hline
|
\hline
|
Script files & \\
|
Script files & \\
|
Build\_TDM\_cont.csh & NC-sim build all files script\\
|
Build\_TDM\_cont.csh & NC-sim build all files script\\
|
cds.lib & NC-sim configuration file\\
|
cds.lib & NC-sim configuration file\\
|
hdl.var & NC-sim configuration file\\
|
hdl.var & NC-sim configuration file\\
|
\hline
|
\hline
|
Test Bench files & \\
|
Test Bench files & \\
|
tdm\_cont\_top.vhd & TDM controller Top test bench\\
|
tdm\_cont\_top.vhd & TDM controller Top test bench\\
|
\hline
|
\hline
|
ISDN controller & \\
|
ISDN controller & \\
|
ISDN\_cont.vhd & Serial Interface\\
|
ISDN\_cont.vhd & Serial Interface\\
|
ISDN\_cont\_top.vhd & ISDN top block\\
|
ISDN\_cont\_top.vhd & ISDN top block\\
|
\hline
|
\hline
|
\end{tabular}
|
\end{tabular}
|
Notes: in order to implement the ISDN controller HDLC core files must be included.
|
Notes: in order to implement the ISDN controller HDLC core files must be included.
|
The following memory cores files must be included to implement the buffers: tools\_pkg.vhd , mem\_pkg.vhd and spmem.vhd
|
The following memory cores files must be included to implement the buffers: tools\_pkg.vhd , mem\_pkg.vhd and spmem.vhd
|
|
|
%%- New section -%%
|
%%- New section -%%
|
%%------------------------------------------%%
|
%%------------------------------------------%%
|
\section{Reviews and comments}
|
\section{Reviews and comments}
|
|
|
%%- New section -%%
|
%%- New section -%%
|
%%------------------------------------------%%
|
%%------------------------------------------%%
|
\section{References}
|
\section{References}
|
|
|
|
|
\end{document}
|
\end{document}
|
|
|
