Subversion Repositories tg68kc

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--                                                                          --

--                                                                          --

-- Copyright (c) 2009-2019 Tobias Gubener                                   -- 

-- Copyright (c) 2009-2019 Tobias Gubener                                   -- 

-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --

-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --

-- Subdesign fAMpIGA by TobiFlex                                            --

-- Subdesign fAMpIGA by TobiFlex                                            --

--                                                                          --

--                                                                          --

-- This source file is free software: you can redistribute it and/or modify --

-- This source file is free software: you can redistribute it and/or modify --

-- it under the terms of the GNU Lesser General Public License as published --

-- it under the terms of the GNU Lesser General Public License as published --

-- by the Free Software Foundation, either version 3 of the License, or     --

-- by the Free Software Foundation, either version 3 of the License, or     --

-- (at your option) any later version.                                      --

-- (at your option) any later version.                                      --

--                                                                          --

--                                                                          --

-- This source file is distributed in the hope that it will be useful,      --

-- This source file is distributed in the hope that it will be useful,      --

-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --

-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --

-- GNU General Public License for more details.                             --

-- GNU General Public License for more details.                             --

--                                                                          --

--                                                                          --

-- You should have received a copy of the GNU General Public License        --

-- You should have received a copy of the GNU General Public License        --

-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --

-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --

--                                                                          --

--                                                                          --

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-- 08.11.2019 TG bugfix movem in 68020 mode

-- 08.11.2019 TG bugfix movem in 68020 mode

-- 06.11.2019 TG bugfix CHK

-- 06.11.2019 TG bugfix CHK

-- 06.11.2019 TG bugfix flags and stackframe DIVU

-- 06.11.2019 TG bugfix flags and stackframe DIVU

-- 04.11.2019 TG insert RTE from TH

-- 04.11.2019 TG insert RTE from TH

-- 03.11.2019 TG insert TrapV from TH 

-- 03.11.2019 TG insert TrapV from TH 

-- 03.11.2019 TG bugfix MUL 64Bit 

-- 03.11.2019 TG bugfix MUL 64Bit 

-- 03.11.2019 TG rework barrel shifter - some other tweaks

-- 03.11.2019 TG rework barrel shifter - some other tweaks

-- 02.11.2019 TG bugfig N-Flag and Z-Flag for DIV

-- 02.11.2019 TG bugfig N-Flag and Z-Flag for DIV

-- 30.10.2019 TG bugfix RTR in 68020-mode

-- 30.10.2019 TG bugfix RTR in 68020-mode

-- 30.10.2019 TG bugfix BFINS again

-- 30.10.2019 TG bugfix BFINS again

-- 19.10.2019 TG insert some bugfixes from apolkosnik

-- 19.10.2019 TG insert some bugfixes from apolkosnik

-- 05.12.2018 TG insert RTD opcode

-- 05.12.2018 TG insert RTD opcode

-- 03.12.2018 TG insert barrel shifter

-- 03.12.2018 TG insert barrel shifter

-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf

-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf

-- 29.05.2017 TG decode 0x4AFB as illegal, needed for QL BKP - thanks Peter Graf

-- 29.05.2017 TG decode 0x4AFB as illegal, needed for QL BKP - thanks Peter Graf

-- 21.05.2017 TG insert generic for hardware multiplier for MULU & MULS

-- 21.05.2017 TG insert generic for hardware multiplier for MULU & MULS

-- 04.04.2017 TG change GPL to LGPL

-- 04.04.2017 TG change GPL to LGPL

-- 04.04.2017 TG BCD handling with all undefined behavior! 

-- 04.04.2017 TG BCD handling with all undefined behavior! 

-- 02.04.2017 TG bugfix Bitfield Opcodes 

-- 02.04.2017 TG bugfix Bitfield Opcodes 

-- 19.03.2017 TG insert PACK/UNPACK  

-- 19.03.2017 TG insert PACK/UNPACK  

-- 19.03.2017 TG bugfix CMPI ...(PC) - thanks Till Harbaum

-- 19.03.2017 TG bugfix CMPI ...(PC) - thanks Till Harbaum

--     ???    MJ bugfix non_aligned movem access

--     ???    MJ bugfix non_aligned movem access

-- add berr handling 10.03.2013 - needed for ATARI Core

-- add berr handling 10.03.2013 - needed for ATARI Core

-- bugfix session 07/08.Feb.2013

-- bugfix session 07/08.Feb.2013

-- movem ,-(an)

-- movem ,-(an)

-- movem (an)+,          - thanks  Gerhard Suttner

-- movem (an)+,          - thanks  Gerhard Suttner

-- btst dn,#data         - thanks  Peter Graf

-- btst dn,#data         - thanks  Peter Graf

-- movep                 - thanks  Till Harbaum

-- movep                 - thanks  Till Harbaum

-- IPL vector            - thanks  Till Harbaum

-- IPL vector            - thanks  Till Harbaum

--  

--  

-- optimize Register file

-- optimize Register file

-- to do 68010:

-- to do 68010:

-- (MOVEC)

-- (MOVEC)

-- BKPT

-- BKPT

-- MOVES

-- MOVES

--

--

-- to do 68020:

-- to do 68020:

-- (CALLM)

-- (CALLM)

-- (RETM)

-- (RETM)

-- CHK2

-- CHK2

-- CMP2

-- CMP2

-- cpXXX Coprozessor stuff

-- cpXXX Coprozessor stuff

-- done 020:

-- done 020:

-- TRAPcc

-- TRAPcc

-- PACK

-- PACK

-- UNPK

-- UNPK

-- Bitfields

-- Bitfields

-- address modes

-- address modes

-- long bra

-- long bra

-- DIVS.L, DIVU.L

-- DIVS.L, DIVU.L

-- LINK long

-- LINK long

-- MULS.L, MULU.L

-- MULS.L, MULU.L

-- extb.l

-- extb.l

library ieee;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_unsigned.all;

use work.TG68K_Pack.all;

use work.TG68K_Pack.all;

entity TG68KdotC_Kernel is

entity TG68KdotC_Kernel is

        generic(

        generic(

                SR_Read : integer:= 2;                          --0=>user,              1=>privileged,          2=>switchable with CPU(0)

                SR_Read : integer:= 2;                          --0=>user,              1=>privileged,          2=>switchable with CPU(0)

                VBR_Stackframe : integer:= 2;           --0=>no,                        1=>yes/extended,        2=>switchable with CPU(0)

                VBR_Stackframe : integer:= 2;           --0=>no,                        1=>yes/extended,        2=>switchable with CPU(0)

                extAddr_Mode : integer:= 2;             --0=>no,                        1=>yes,                         2=>switchable with CPU(1)

                extAddr_Mode : integer:= 2;             --0=>no,                        1=>yes,                         2=>switchable with CPU(1)

                MUL_Mode : integer := 2;                        --0=>16Bit,             1=>32Bit,                       2=>switchable with CPU(1),  3=>no MUL,  

                MUL_Mode : integer := 2;                        --0=>16Bit,             1=>32Bit,                       2=>switchable with CPU(1),  3=>no MUL,  

                DIV_Mode : integer := 2;                        --0=>16Bit,             1=>32Bit,                       2=>switchable with CPU(1),  3=>no DIV,  

                DIV_Mode : integer := 2;                        --0=>16Bit,             1=>32Bit,                       2=>switchable with CPU(1),  3=>no DIV,  

                BitField : integer := 2;                        --0=>no,                        1=>yes,                         2=>switchable with CPU(1) 

                BitField : integer := 2;                        --0=>no,                        1=>yes,                         2=>switchable with CPU(1) 

                BarrelShifter : integer := 1;           --0=>no,                        1=>yes,                         2=>switchable with CPU(1)  

                BarrelShifter : integer := 1;           --0=>no,                        1=>yes,                         2=>switchable with CPU(1)  

                MUL_Hardware : integer := 1             --0=>no,                        1=>yes,  

                MUL_Hardware : integer := 1             --0=>no,                        1=>yes,  

                );

                );

        port(clk                                                : in std_logic;

        port(clk                                                : in std_logic;

                nReset                                  : in std_logic;                 --low active

                nReset                                  : in std_logic;                 --low active

                clkena_in                               : in std_logic:='1';

                clkena_in                               : in std_logic:='1';

                data_in                                 : in std_logic_vector(15 downto 0);

                data_in                                 : in std_logic_vector(15 downto 0);

                IPL                                             : in std_logic_vector(2 downto 0):="111";

                IPL                                             : in std_logic_vector(2 downto 0):="111";

                IPL_autovector                  : in std_logic:='0';

                IPL_autovector                  : in std_logic:='0';

                berr                                            : in std_logic:='0';                                     -- only 68000 Stackpointer dummy

                berr                                            : in std_logic:='0';                                     -- only 68000 Stackpointer dummy

                CPU                                             : in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)

                CPU                                             : in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)

                addr_out                                        : out std_logic_vector(31 downto 0);

                addr_out                                        : out std_logic_vector(31 downto 0);

                data_write                              : out std_logic_vector(15 downto 0);

                data_write                              : out std_logic_vector(15 downto 0);

                nWr                                             : out std_logic;

                nWr                                             : out std_logic;

                nUDS                                            : out std_logic;

                nUDS                                            : out std_logic;

                nLDS                                            : out std_logic;

                nLDS                                            : out std_logic;

                busstate                                        : out std_logic_vector(1 downto 0);      -- 00-> fetch code 10->read data 11->write data 01->no memaccess

                busstate                                        : out std_logic_vector(1 downto 0);      -- 00-> fetch code 10->read data 11->write data 01->no memaccess

                nResetOut                               : out std_logic;

                nResetOut                               : out std_logic;

                FC                                                      : out std_logic_vector(2 downto 0);

                FC                                                      : out std_logic_vector(2 downto 0);

                clr_berr                                        : out std_logic;

                clr_berr                                        : out std_logic;

-- for debug

-- for debug

                skipFetch                               : out std_logic;

                skipFetch                               : out std_logic;

                regin_out                               : out std_logic_vector(31 downto 0);

                regin_out                               : out std_logic_vector(31 downto 0);

                CACR_out                                        : out std_logic_vector( 3 downto 0);

                CACR_out                                        : out std_logic_vector( 3 downto 0);

                VBR_out                                 : out std_logic_vector(31 downto 0)

                VBR_out                                 : out std_logic_vector(31 downto 0)

                );

                );

end TG68KdotC_Kernel;

end TG68KdotC_Kernel;

architecture logic of TG68KdotC_Kernel is

architecture logic of TG68KdotC_Kernel is

        signal use_VBR_Stackframe       : std_logic;

        signal use_VBR_Stackframe       : std_logic;

        signal syncReset                        : std_logic_vector(3 downto 0);

        signal syncReset                        : std_logic_vector(3 downto 0);

        signal Reset                            : std_logic;

        signal Reset                            : std_logic;

        signal clkena_lw                        : std_logic;

        signal clkena_lw                        : std_logic;

        signal TG68_PC                          : std_logic_vector(31 downto 0);

        signal TG68_PC                          : std_logic_vector(31 downto 0);

        signal tmp_TG68_PC              : std_logic_vector(31 downto 0);

        signal tmp_TG68_PC              : std_logic_vector(31 downto 0);

        signal TG68_PC_add              : std_logic_vector(31 downto 0);

        signal TG68_PC_add              : std_logic_vector(31 downto 0);

        signal PC_dataa                 : std_logic_vector(31 downto 0);

        signal PC_dataa                 : std_logic_vector(31 downto 0);

        signal PC_datab                 : std_logic_vector(31 downto 0);

        signal PC_datab                 : std_logic_vector(31 downto 0);

        signal memaddr                          : std_logic_vector(31 downto 0);

        signal memaddr                          : std_logic_vector(31 downto 0);

        signal state                            : std_logic_vector(1 downto 0);

        signal state                            : std_logic_vector(1 downto 0);

        signal datatype                 : std_logic_vector(1 downto 0);

        signal datatype                 : std_logic_vector(1 downto 0);

        signal set_datatype             : std_logic_vector(1 downto 0);

        signal set_datatype             : std_logic_vector(1 downto 0);

        signal exe_datatype             : std_logic_vector(1 downto 0);

        signal exe_datatype             : std_logic_vector(1 downto 0);

        signal setstate                 : std_logic_vector(1 downto 0);

        signal setstate                 : std_logic_vector(1 downto 0);

        signal opcode                           : std_logic_vector(15 downto 0);

        signal opcode                           : std_logic_vector(15 downto 0);

        signal exe_opcode                       : std_logic_vector(15 downto 0);

        signal exe_opcode                       : std_logic_vector(15 downto 0);

        signal sndOPC                           : std_logic_vector(15 downto 0);

        signal sndOPC                           : std_logic_vector(15 downto 0);

        signal exe_pc                           : std_logic_vector(31 downto 0);--TH

        signal exe_pc                           : std_logic_vector(31 downto 0);--TH

        signal last_opc_pc              : std_logic_vector(31 downto 0);--TH

        signal last_opc_pc              : std_logic_vector(31 downto 0);--TH

        signal last_opc_read            : std_logic_vector(15 downto 0);

        signal last_opc_read            : std_logic_vector(15 downto 0);

        signal registerin                       : std_logic_vector(31 downto 0);

        signal registerin                       : std_logic_vector(31 downto 0);

        signal reg_QA                           : std_logic_vector(31 downto 0);

        signal reg_QA                           : std_logic_vector(31 downto 0);

        signal reg_QB                           : std_logic_vector(31 downto 0);

        signal reg_QB                           : std_logic_vector(31 downto 0);

        signal Wwrena,Lwrena            : bit;

        signal Wwrena,Lwrena            : bit;

        signal Bwrena                           : bit;

        signal Bwrena                           : bit;

        signal Regwrena_now             : bit;

        signal Regwrena_now             : bit;

        signal rf_dest_addr             : std_logic_vector(3 downto 0);

        signal rf_dest_addr             : std_logic_vector(3 downto 0);

        signal rf_source_addr   : std_logic_vector(3 downto 0);

        signal rf_source_addr   : std_logic_vector(3 downto 0);

        signal rf_source_addrd  : std_logic_vector(3 downto 0);

        signal rf_source_addrd  : std_logic_vector(3 downto 0);

        signal regin                            : std_logic_vector(31 downto 0);

        signal regin                            : std_logic_vector(31 downto 0);

        type   regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);

        type   regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);

        signal regfile                          : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;

        signal regfile                          : regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;

        signal RDindex_A                        : integer range 0 to 15;

        signal RDindex_A                        : integer range 0 to 15;

        signal RDindex_B                        : integer range 0 to 15;

        signal RDindex_B                        : integer range 0 to 15;

        signal WR_AReg                          : std_logic;

        signal WR_AReg                          : std_logic;

        signal addr                                     : std_logic_vector(31 downto 0);

        signal addr                                     : std_logic_vector(31 downto 0);

        signal memaddr_reg              : std_logic_vector(31 downto 0);

        signal memaddr_reg              : std_logic_vector(31 downto 0);

        signal memaddr_delta            : std_logic_vector(31 downto 0);

        signal memaddr_delta            : std_logic_vector(31 downto 0);

        signal use_base                 : bit;

        signal use_base                 : bit;

        signal ea_data                          : std_logic_vector(31 downto 0);

        signal ea_data                          : std_logic_vector(31 downto 0);

        signal OP1out                           : std_logic_vector(31 downto 0);

        signal OP1out                           : std_logic_vector(31 downto 0);

        signal OP2out                           : std_logic_vector(31 downto 0);

        signal OP2out                           : std_logic_vector(31 downto 0);

        signal OP1outbrief              : std_logic_vector(15 downto 0);

        signal OP1outbrief              : std_logic_vector(15 downto 0);

        signal OP1in                            : std_logic_vector(31 downto 0);

        signal OP1in                            : std_logic_vector(31 downto 0);

        signal ALUout   : std_logic_vector(31 downto 0);

        signal ALUout   : std_logic_vector(31 downto 0);

        signal data_write_tmp   : std_logic_vector(31 downto 0);

        signal data_write_tmp   : std_logic_vector(31 downto 0);

        signal data_write_muxin : std_logic_vector(31 downto 0);

        signal data_write_muxin : std_logic_vector(31 downto 0);

        signal data_write_mux   : std_logic_vector(47 downto 0);

        signal data_write_mux   : std_logic_vector(47 downto 0);

        signal nextpass                 : bit;

        signal nextpass                 : bit;

        signal setnextpass              : bit;

        signal setnextpass              : bit;

        signal setdispbyte              : bit;

        signal setdispbyte              : bit;

        signal setdisp                          : bit;

        signal setdisp                          : bit;

        signal regdirectsource  :bit;           -- checken !!!

        signal regdirectsource  :bit;           -- checken !!!

        signal addsub_q                 : std_logic_vector(31 downto 0);

        signal addsub_q                 : std_logic_vector(31 downto 0);

        signal briefdata                        : std_logic_vector(31 downto 0);

        signal briefdata                        : std_logic_vector(31 downto 0);

--      signal c_in                             : std_logic_vector(3 downto 0);

--      signal c_in                             : std_logic_vector(3 downto 0);

        signal c_out                            : std_logic_vector(2 downto 0);

        signal c_out                            : std_logic_vector(2 downto 0);

        signal mem_address              : std_logic_vector(31 downto 0);

        signal mem_address              : std_logic_vector(31 downto 0);

        signal memaddr_a                        : std_logic_vector(31 downto 0);

        signal memaddr_a                        : std_logic_vector(31 downto 0);

        signal TG68_PC_brw              : bit;

        signal TG68_PC_brw              : bit;

        signal TG68_PC_word             : bit;

        signal TG68_PC_word             : bit;

        signal getbrief                 : bit;

        signal getbrief                 : bit;

        signal brief                            : std_logic_vector(15 downto 0);

        signal brief                            : std_logic_vector(15 downto 0);

        signal data_is_source   : bit;

        signal data_is_source   : bit;

        signal store_in_tmp             : bit;

        signal store_in_tmp             : bit;

        signal write_back                       : bit;

        signal write_back                       : bit;

        signal exec_write_back  : bit;

        signal exec_write_back  : bit;

        signal setstackaddr             : bit;

        signal setstackaddr             : bit;

        signal writePC                          : bit;

        signal writePC                          : bit;

        signal writePCbig                       : bit;

        signal writePCbig                       : bit;

        signal set_writePCbig   : bit;

        signal set_writePCbig   : bit;

        signal setopcode                        : bit;

        signal setopcode                        : bit;

        signal decodeOPC                        : bit;

        signal decodeOPC                        : bit;

        signal execOPC                          : bit;

        signal execOPC                          : bit;

        signal setexecOPC                       : bit;

        signal setexecOPC                       : bit;

        signal endOPC                           : bit;

        signal endOPC                           : bit;

        signal setendOPC                        : bit;

        signal setendOPC                        : bit;

        signal Flags                            : std_logic_vector(7 downto 0);  -- ...XNZVC

        signal Flags                            : std_logic_vector(7 downto 0);  -- ...XNZVC

        signal FlagsSR                          : std_logic_vector(7 downto 0);  -- T.S.0III

        signal FlagsSR                          : std_logic_vector(7 downto 0);  -- T.S.0III

        signal SRin                                     : std_logic_vector(7 downto 0);

        signal SRin                                     : std_logic_vector(7 downto 0);

        signal exec_DIRECT              : bit;

        signal exec_DIRECT              : bit;

        signal exec_tas                 : std_logic;

        signal exec_tas                 : std_logic;

        signal set_exec_tas             : std_logic;

        signal set_exec_tas             : std_logic;

        signal exe_condition            : std_logic;

        signal exe_condition            : std_logic;

        signal ea_only                          : bit;

        signal ea_only                          : bit;

        signal source_lowbits   : bit;

        signal source_lowbits   : bit;

        signal source_2ndHbits  : bit;

        signal source_2ndHbits  : bit;

        signal source_2ndLbits  : bit;

        signal source_2ndLbits  : bit;

        signal dest_2ndHbits            : bit;

        signal dest_2ndHbits            : bit;

        signal dest_hbits                       : bit;

        signal dest_hbits                       : bit;

        signal rot_bits                 : std_logic_vector(1 downto 0);

        signal rot_bits                 : std_logic_vector(1 downto 0);

        signal set_rot_bits             : std_logic_vector(1 downto 0);

        signal set_rot_bits             : std_logic_vector(1 downto 0);

        signal rot_cnt                          : std_logic_vector(5 downto 0);

        signal rot_cnt                          : std_logic_vector(5 downto 0);

        signal set_rot_cnt              : std_logic_vector(5 downto 0);

        signal set_rot_cnt              : std_logic_vector(5 downto 0);

        signal movem_actiond            : bit;

        signal movem_actiond            : bit;

        signal movem_regaddr            : std_logic_vector(3 downto 0);

        signal movem_regaddr            : std_logic_vector(3 downto 0);

        signal movem_mux                        : std_logic_vector(3 downto 0);

        signal movem_mux                        : std_logic_vector(3 downto 0);

        signal movem_presub             : bit;

        signal movem_presub             : bit;

        signal movem_run                        : bit;

        signal movem_run                        : bit;

        signal ea_calc_b                        : std_logic_vector(31 downto 0);

        signal ea_calc_b                        : std_logic_vector(31 downto 0);

        signal set_direct_data  : bit;

        signal set_direct_data  : bit;

        signal use_direct_data  : bit;

        signal use_direct_data  : bit;

        signal direct_data              : bit;

        signal direct_data              : bit;

        signal set_V_Flag                       : bit;

        signal set_V_Flag                       : bit;

        signal set_vectoraddr   : bit;

        signal set_vectoraddr   : bit;

        signal writeSR                          : bit;

        signal writeSR                          : bit;

        signal trap_berr                        : bit;

        signal trap_berr                        : bit;

        signal trap_illegal             : bit;

        signal trap_illegal             : bit;

        signal trap_addr_error  : bit;

        signal trap_addr_error  : bit;

        signal trap_priv                        : bit;

        signal trap_priv                        : bit;

        signal trap_trace                       : bit;

        signal trap_trace                       : bit;

        signal trap_1010                        : bit;

        signal trap_1010                        : bit;

        signal trap_1111                        : bit;

        signal trap_1111                        : bit;

        signal trap_trap                        : bit;

        signal trap_trap                        : bit;

        signal trap_trapv                       : bit;

        signal trap_trapv                       : bit;

        signal trap_interrupt   : bit;

        signal trap_interrupt   : bit;

        signal trapmake                 : bit;

        signal trapmake                 : bit;

        signal trapd                            : bit;

        signal trapd                            : bit;

        signal trap_SR                          : std_logic_vector(7 downto 0);

        signal trap_SR                          : std_logic_vector(7 downto 0);

        signal make_trace                       : std_logic;

        signal make_trace                       : std_logic;

        signal make_berr                        : std_logic;

        signal make_berr                        : std_logic;

        signal useStackframe2   : std_logic;

        signal useStackframe2   : std_logic;

        signal set_stop                 : bit;

        signal set_stop                 : bit;

        signal stop                                     : bit;

        signal stop                                     : bit;

        signal trap_vector              : std_logic_vector(31 downto 0);

        signal trap_vector              : std_logic_vector(31 downto 0);

        signal trap_vector_vbr  : std_logic_vector(31 downto 0);

        signal trap_vector_vbr  : std_logic_vector(31 downto 0);

        signal USP                                      : std_logic_vector(31 downto 0);

        signal USP                                      : std_logic_vector(31 downto 0);

--      signal illegal_write_mode       : bit;

--      signal illegal_write_mode       : bit;

--      signal illegal_read_mode        : bit;

--      signal illegal_read_mode        : bit;

--      signal illegal_byteaddr         : bit;

--      signal illegal_byteaddr         : bit;

        signal IPL_nr                           : std_logic_vector(2 downto 0);

        signal IPL_nr                           : std_logic_vector(2 downto 0);

        signal rIPL_nr                          : std_logic_vector(2 downto 0);

        signal rIPL_nr                          : std_logic_vector(2 downto 0);

        signal IPL_vec                          : std_logic_vector(7 downto 0);

        signal IPL_vec                          : std_logic_vector(7 downto 0);

        signal interrupt                        : bit;

        signal interrupt                        : bit;

        signal setinterrupt             : bit;

        signal setinterrupt             : bit;

        signal SVmode                           : std_logic;

        signal SVmode                           : std_logic;

        signal preSVmode                        : std_logic;

        signal preSVmode                        : std_logic;

        signal Suppress_Base            : bit;

        signal Suppress_Base            : bit;

        signal set_Suppress_Base: bit;

        signal set_Suppress_Base: bit;

        signal set_Z_error              : bit;

        signal set_Z_error              : bit;

        signal Z_error                  : bit;

        signal Z_error                  : bit;

        signal ea_build_now             : bit;

        signal ea_build_now             : bit;

        signal build_logical            : bit;

        signal build_logical            : bit;

        signal build_bcd                        : bit;

        signal build_bcd                        : bit;

        signal data_read                        : std_logic_vector(31 downto 0);

        signal data_read                        : std_logic_vector(31 downto 0);

        signal bf_ext_in                        : std_logic_vector(7 downto 0);

        signal bf_ext_in                        : std_logic_vector(7 downto 0);

        signal bf_ext_out                       : std_logic_vector(7 downto 0);

        signal bf_ext_out                       : std_logic_vector(7 downto 0);

--      signal byte                                     : bit;

--      signal byte                                     : bit;

        signal long_start                       : bit;

        signal long_start                       : bit;

        signal long_start_alu   : bit;

        signal long_start_alu   : bit;

        signal non_aligned              : std_logic;

        signal non_aligned              : std_logic;

        signal long_done                        : bit;

        signal long_done                        : bit;

        signal memmask                          : std_logic_vector(5 downto 0);

        signal memmask                          : std_logic_vector(5 downto 0);

        signal set_memmask              : std_logic_vector(5 downto 0);

        signal set_memmask              : std_logic_vector(5 downto 0);

        signal memread                          : std_logic_vector(3 downto 0);

        signal memread                          : std_logic_vector(3 downto 0);

        signal wbmemmask                        : std_logic_vector(5 downto 0);

        signal wbmemmask                        : std_logic_vector(5 downto 0);

        signal memmaskmux                       : std_logic_vector(5 downto 0);

        signal memmaskmux                       : std_logic_vector(5 downto 0);

        signal oddout                           : std_logic;

        signal oddout                           : std_logic;

        signal set_oddout                       : std_logic;

        signal set_oddout                       : std_logic;

        signal PCbase                           : std_logic;

        signal PCbase                           : std_logic;

        signal set_PCbase                       : std_logic;

        signal set_PCbase                       : std_logic;

        signal last_data_read   : std_logic_vector(31 downto 0);

        signal last_data_read   : std_logic_vector(31 downto 0);

        signal last_data_in             : std_logic_vector(31 downto 0);

        signal last_data_in             : std_logic_vector(31 downto 0);

        signal bf_offset                        : std_logic_vector(5 downto 0);

        signal bf_offset                        : std_logic_vector(5 downto 0);

        signal bf_width                 : std_logic_vector(5 downto 0);

        signal bf_width                 : std_logic_vector(5 downto 0);

        signal bf_bhits                 : std_logic_vector(5 downto 0);

        signal bf_bhits                 : std_logic_vector(5 downto 0);

        signal bf_shift                 : std_logic_vector(5 downto 0);

        signal bf_shift                 : std_logic_vector(5 downto 0);

        signal alu_width                        : std_logic_vector(5 downto 0);

        signal alu_width                        : std_logic_vector(5 downto 0);

        signal alu_bf_shift             : std_logic_vector(5 downto 0);

        signal alu_bf_shift             : std_logic_vector(5 downto 0);

        signal bf_loffset                       : std_logic_vector(5 downto 0);

        signal bf_loffset                       : std_logic_vector(5 downto 0);

        signal bf_full_offset   : std_logic_vector(31 downto 0);

        signal bf_full_offset   : std_logic_vector(31 downto 0);

        signal alu_bf_ffo_offset: std_logic_vector(31 downto 0);

        signal alu_bf_ffo_offset: std_logic_vector(31 downto 0);

        signal alu_bf_loffset   : std_logic_vector(5 downto 0);

        signal alu_bf_loffset   : std_logic_vector(5 downto 0);

        signal movec_data                       : std_logic_vector(31 downto 0);

        signal movec_data                       : std_logic_vector(31 downto 0);

        signal VBR                                      : std_logic_vector(31 downto 0);

        signal VBR                                      : std_logic_vector(31 downto 0);

        signal CACR                                     : std_logic_vector(3 downto 0);

        signal CACR                                     : std_logic_vector(3 downto 0);

        signal DFC                                      : std_logic_vector(2 downto 0);

        signal DFC                                      : std_logic_vector(2 downto 0);

        signal SFC                                      : std_logic_vector(2 downto 0);

        signal SFC                                      : std_logic_vector(2 downto 0);

        signal set                                      : bit_vector(lastOpcBit downto 0);

        signal set                                      : bit_vector(lastOpcBit downto 0);

        signal set_exec                 : bit_vector(lastOpcBit downto 0);

        signal set_exec                 : bit_vector(lastOpcBit downto 0);

        signal exec                                     : bit_vector(lastOpcBit downto 0);

        signal exec                                     : bit_vector(lastOpcBit downto 0);

        signal micro_state              : micro_states;

        signal micro_state              : micro_states;

        signal next_micro_state : micro_states;

        signal next_micro_state : micro_states;

BEGIN

BEGIN

ALU: TG68K_ALU

ALU: TG68K_ALU

        generic map(

        generic map(

                MUL_Mode => MUL_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no MUL,

                MUL_Mode => MUL_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no MUL,

                MUL_Hardware => MUL_Hardware,           --0=>no,                1=>yes,

                MUL_Hardware => MUL_Hardware,           --0=>no,                1=>yes,

                DIV_Mode => DIV_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no DIV,

                DIV_Mode => DIV_Mode,                           --0=>16Bit,     1=>32Bit,       2=>switchable with CPU(1),              3=>no DIV,

                BarrelShifter => BarrelShifter  --0=>no,                1=>yes,         2=>switchable with CPU(1)  

                BarrelShifter => BarrelShifter  --0=>no,                1=>yes,         2=>switchable with CPU(1)  

                )

                )

        port map(

        port map(

                clk => clk,                                                             --: in std_logic;

                clk => clk,                                                             --: in std_logic;

                Reset => Reset,                                         --: in std_logic;

                Reset => Reset,                                         --: in std_logic;

                clkena_lw => clkena_lw,                         --: in std_logic:='1';

                clkena_lw => clkena_lw,                         --: in std_logic:='1';

                decodeOPC => decodeOPC,                         --: in bit;

                decodeOPC => decodeOPC,                         --: in bit;

                exe_condition => exe_condition, --: in std_logic;

                exe_condition => exe_condition, --: in std_logic;

                exec_tas => exec_tas,                           --: in std_logic;

                exec_tas => exec_tas,                           --: in std_logic;

                long_start => long_start_alu,           --: in bit;

                long_start => long_start_alu,           --: in bit;

                non_aligned => non_aligned,

                non_aligned => non_aligned,

                movem_presub => movem_presub,           --: in bit;

                movem_presub => movem_presub,           --: in bit;

                set_stop => set_stop,                           --: in bit;

                set_stop => set_stop,                           --: in bit;

                Z_error => Z_error,                                     --: in bit;

                Z_error => Z_error,                                     --: in bit;

                rot_bits => rot_bits,                           --: in std_logic_vector(1 downto 0);

                rot_bits => rot_bits,                           --: in std_logic_vector(1 downto 0);

                exec => exec,                                                   --: in bit_vector(lastOpcBit downto 0);

                exec => exec,                                                   --: in bit_vector(lastOpcBit downto 0);

                OP1out => OP1out,                                               --: in std_logic_vector(31 downto 0);

                OP1out => OP1out,                                               --: in std_logic_vector(31 downto 0);

                OP2out => OP2out,                                               --: in std_logic_vector(31 downto 0);

                OP2out => OP2out,                                               --: in std_logic_vector(31 downto 0);

                reg_QA => reg_QA,                                               --: in std_logic_vector(31 downto 0);

                reg_QA => reg_QA,                                               --: in std_logic_vector(31 downto 0);

                reg_QB => reg_QB,                                               --: in std_logic_vector(31 downto 0);

                reg_QB => reg_QB,                                               --: in std_logic_vector(31 downto 0);

                opcode => opcode,                                               --: in std_logic_vector(15 downto 0);

                opcode => opcode,                                               --: in std_logic_vector(15 downto 0);

                exe_opcode => exe_opcode,                       --: in std_logic_vector(15 downto 0);

                exe_opcode => exe_opcode,                       --: in std_logic_vector(15 downto 0);

                exe_datatype => exe_datatype,           --: in std_logic_vector(1 downto 0);

                exe_datatype => exe_datatype,           --: in std_logic_vector(1 downto 0);

                sndOPC => sndOPC,                                               --: in std_logic_vector(15 downto 0);

                sndOPC => sndOPC,                                               --: in std_logic_vector(15 downto 0);

                last_data_read => last_data_read(15 downto 0),   --: in std_logic_vector(31 downto 0);

                last_data_read => last_data_read(15 downto 0),   --: in std_logic_vector(31 downto 0);

                data_read => data_read(15 downto 0),                             --: in std_logic_vector(31 downto 0);

                data_read => data_read(15 downto 0),                             --: in std_logic_vector(31 downto 0);

                FlagsSR => FlagsSR,                                     --: in std_logic_vector(7 downto 0);

                FlagsSR => FlagsSR,                                     --: in std_logic_vector(7 downto 0);

                micro_state => micro_state,             --: in micro_states;  

                micro_state => micro_state,             --: in micro_states;  

                bf_ext_in => bf_ext_in,

                bf_ext_in => bf_ext_in,

                bf_ext_out => bf_ext_out,

                bf_ext_out => bf_ext_out,

                bf_shift => alu_bf_shift,

                bf_shift => alu_bf_shift,

                bf_width => alu_width,

                bf_width => alu_width,

                bf_ffo_offset => alu_bf_ffo_offset,

                bf_ffo_offset => alu_bf_ffo_offset,

                bf_loffset => alu_bf_loffset(4 downto 0),

                bf_loffset => alu_bf_loffset(4 downto 0),

                set_V_Flag => set_V_Flag,                       --: buffer bit;

                set_V_Flag => set_V_Flag,                       --: buffer bit;

                Flags => Flags,                                         --: buffer std_logic_vector(8 downto 0);

                Flags => Flags,                                         --: buffer std_logic_vector(8 downto 0);

                c_out => c_out,                                         --: buffer std_logic_vector(2 downto 0);

                c_out => c_out,                                         --: buffer std_logic_vector(2 downto 0);

                addsub_q => addsub_q,                           --: buffer std_logic_vector(31 downto 0);

                addsub_q => addsub_q,                           --: buffer std_logic_vector(31 downto 0);

                ALUout => ALUout                                                --: buffer std_logic_vector(31 downto 0)

                ALUout => ALUout                                                --: buffer std_logic_vector(31 downto 0)

        );

        );

        long_start_alu <= to_bit(NOT memmaskmux(3));

        long_start_alu <= to_bit(NOT memmaskmux(3));

        process (memmaskmux)

        process (memmaskmux)

        begin

        begin

                non_aligned <= '0';

                non_aligned <= '0';

                if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then

                if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then

                        non_aligned <= '1';

                        non_aligned <= '1';

                end if;

                end if;

        end process;

        end process;

-----------------------------------------------------------------------------

-----------------------------------------------------------------------------

-- Bus control

-- Bus control

-----------------------------------------------------------------------------

-----------------------------------------------------------------------------

   regin_out <= regin;

   regin_out <= regin;

        nWr <= '0' WHEN state="11" ELSE '1';

        nWr <= '0' WHEN state="11" ELSE '1';

        busstate <= state;

        busstate <= state;

        nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';

        nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';

        -- does shift for byte access. note active low me

        -- does shift for byte access. note active low me

        -- should produce address error on 68000

        -- should produce address error on 68000

        memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';

        memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';

        nUDS <= memmaskmux(5);

        nUDS <= memmaskmux(5);

        nLDS <= memmaskmux(4);

        nLDS <= memmaskmux(4);

        clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';

        clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';

        clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';

        clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';

        PROCESS (clk, nReset)

        PROCESS (clk, nReset)

        BEGIN

        BEGIN

                IF nReset='0' THEN

                IF nReset='0' THEN

                        syncReset <= "0000";

                        syncReset <= "0000";

                        Reset <= '1';