`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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|
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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|
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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|
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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|
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***********************************************************************************/
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***********************************************************************************/
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`define TNF_AFTER_RESET 0
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`define TNF_AFTER_RESET 0
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`define TNF_IDLE 1
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`define TNF_IDLE 1
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`define TNF_REQUEST_AABBMIN 2
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`define TNF_REQUEST_AABBMIN 2
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`define TNF_WAIT_FOR_AABBMIN 3
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`define TNF_WAIT_FOR_AABBMIN 3
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`define TNF_REQUEST_AABBMAX 4
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`define TNF_REQUEST_AABBMAX 4
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`define TNF_WAIT_FOR_AABBMAX 5
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`define TNF_WAIT_FOR_AABBMAX 5
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|
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`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
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`define TNF_REQUEST_NUMBER_OF_TRIANGLES 10
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`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
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`define TNF_WAIT_FOR_NUMBER_OF_TRIANGLES 11
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`define TNF_LATCH_NUMBER_OF_TRIANGLES 12
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`define TNF_LATCH_NUMBER_OF_TRIANGLES 12
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`define TNF_WAIT_NODE_READ_ACK 13
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`define TNF_WAIT_NODE_READ_ACK 13
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`define TNF_REQUEST_DATA_OFFSET 14
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`define TNF_REQUEST_DATA_OFFSET 14
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`define TNF_WAIT_FOR_DATA_OFFSET 15
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`define TNF_WAIT_FOR_DATA_OFFSET 15
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`define TNF_LATCH_DATA_OFFSET 16
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`define TNF_LATCH_DATA_OFFSET 16
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`define TNF_REQUEST_NODE_BROTHER_ADDRESS 17
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`define TNF_REQUEST_NODE_BROTHER_ADDRESS 17
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`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
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`define TNF_WAIT_FOR_NODE_BROTHER_ADDRESS 18
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`define TNF_LACTH_NODE_BROTHER_ADDRESS 19
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`define TNF_LACTH_NODE_BROTHER_ADDRESS 19
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`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
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`define TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS 20
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`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS 21
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`define TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS 21
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`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS 22
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`define TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS 22
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`define TNF_RAM_WRITE_DELAY1 23
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`define TNF_RAM_WRITE_DELAY1 23
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`define TNF_INC1 24
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`define TNF_INC1 24
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`define TNF_INC2 25
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`define TNF_INC2 25
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`define TNF_INC3 26
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`define TNF_INC3 26
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|
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/*
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/*
|
|
|
To fetch node, we need to ask WBM to perform several read cycles.
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To fetch node, we need to ask WBM to perform several read cycles.
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Each read cycle reads 32 bits. The first 6 read cycles requests
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Each read cycle reads 32 bits. The first 6 read cycles requests
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consecutive addresses that represent AABBMAX and AABBMIN corners.
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consecutive addresses that represent AABBMAX and AABBMIN corners.
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These 6 values must be stored into RAM for the ucode to use.
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These 6 values must be stored into RAM for the ucode to use.
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Next value represents the number of vertices this AABB has, or
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Next value represents the number of vertices this AABB has, or
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zero is is not a LEAF.
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zero is is not a LEAF.
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Next value is the offset where of the vertex data.
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Next value is the offset where of the vertex data.
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*/
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*/
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|
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module TreeNodeFetcher
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module TreeNodeFetcher
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire[`WIDTH-1:0] iData,
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input wire[`WIDTH-1:0] iData,
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input wire iDataAvailable,
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input wire iDataAvailable,
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input wire iTrigger,
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input wire iTrigger,
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input wire[`WIDTH-1:0] iInitialAddress,
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input wire[`WIDTH-1:0] iInitialAddress,
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|
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//wires that go into WBM
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//wires that go into WBM
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output reg oSetAddressWBM,
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output reg oSetAddressWBM,
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output reg oEnableWBM,
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output reg oEnableWBM,
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output wire[`WIDTH-1:0] oAddressWBM,
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output wire[`WIDTH-1:0] oAddressWBM,
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//The parsed node info
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//The parsed node info
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output wire oNode_IsLeaf,
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output wire oNode_IsLeaf,
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output wire[`WIDTH-1:0] oNode_DataOffset,
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output wire[`WIDTH-1:0] oNode_DataOffset,
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output wire [`WIDTH-1:0] oNode_TriangleCount, //Change to 16 bits
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output wire [`WIDTH-1:0] oNode_TriangleCount, //Change to 16 bits
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//output wire [`WIDTH-1:0] oNode_ChildCount, //Change to 16 bits
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//output wire [`WIDTH-1:0] oNode_ChildCount, //Change to 16 bits
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|
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output wire [`WIDTH-1:0] oNode_Brother_Address, //*
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output wire [`WIDTH-1:0] oNode_Brother_Address, //*
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output wire [`WIDTH-1:0] oParents_Brother_Address, //*
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output wire [`WIDTH-1:0] oParents_Brother_Address, //*
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//output reg [`WIDTH-1:0] oNode_FirstChild_Address,
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//output reg [`WIDTH-1:0] oNode_FirstChild_Address,
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|
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output reg oNodeReadDone,
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output reg oNodeReadDone,
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output reg oRAMWriteEnable,
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output reg oRAMWriteEnable,
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|
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output reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
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output reg [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress
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);
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);
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|
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reg [4:0] CurrentState;
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reg [4:0] CurrentState;
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reg [4:0] NextState;
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reg [4:0] NextState;
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|
|
|
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assign oAddressWBM = iInitialAddress;
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assign oAddressWBM = iInitialAddress;
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|
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reg rFFEnNumVertices;
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reg rFFEnNumVertices;
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|
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//Flip Flop D
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//Flip Flop D
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//FFD_SYNCH_RST_GENERIC FFD32_TNF
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//FFD_SYNCH_RST_GENERIC FFD32_TNF
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( rFFEnNumVertices ),
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.Enable( rFFEnNumVertices ),
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.D( iData ),
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.D( iData ),
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.Q( oNode_TriangleCount )
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.Q( oNode_TriangleCount )
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|
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);
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);
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|
|
|
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reg rFFEnBrotherAddress;
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reg rFFEnBrotherAddress;
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//Flip Flop D
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//Flip Flop D
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC
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//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC
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//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( rFFEnBrotherAddress ),
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.Enable( rFFEnBrotherAddress ),
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.D( iData ),
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.D( iData ),
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.Q( oNode_Brother_Address )
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.Q( oNode_Brother_Address )
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|
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);
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);
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|
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reg rFFEnParentsBroAddr;
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reg rFFEnParentsBroAddr;
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//Flip Flop D
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//Flip Flop D
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC2
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF_NC2
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//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2
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//FFD_SYNCH_RST_GENERIC FFD32_TNF_NC2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( rFFEnParentsBroAddr ),
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.Enable( rFFEnParentsBroAddr ),
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.D( iData ),
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.D( iData ),
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.Q( oParents_Brother_Address )
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.Q( oParents_Brother_Address )
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|
|
);
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);
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|
|
|
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reg rFFEnDataOffset;
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reg rFFEnDataOffset;
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//Flip Flop D
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//Flip Flop D
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF2
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_TNF2
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//FFD_SYNCH_RST_GENERIC FFD32_TNF2
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//FFD_SYNCH_RST_GENERIC FFD32_TNF2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( rFFEnDataOffset ),
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.Enable( rFFEnDataOffset ),
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.D( iData ),
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.D( iData ),
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.Q( oNode_DataOffset )
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.Q( oNode_DataOffset )
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|
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);
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);
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|
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|
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assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);
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assign oNode_IsLeaf = (oNode_TriangleCount != 32'h0);
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|
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//------------------------------------------------
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//------------------------------------------------
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always @(posedge Clock or posedge Reset)
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always @(posedge Clock or posedge Reset)
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begin
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begin
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|
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if (Reset)
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if (Reset)
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CurrentState <= `TNF_AFTER_RESET;
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CurrentState <= `TNF_AFTER_RESET;
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else
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else
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CurrentState <= NextState;
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CurrentState <= NextState;
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|
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end
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end
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|
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//------------------------------------
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//------------------------------------
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/*
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/*
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IDLE State just waiting for something
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IDLE State just waiting for something
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to do...
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to do...
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*/
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*/
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|
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always @( * )
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always @( * )
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begin
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begin
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case (CurrentState)
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case (CurrentState)
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//------------------------------------
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//------------------------------------
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`TNF_AFTER_RESET:
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`TNF_AFTER_RESET:
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begin
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begin
|
|
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oRAMWriteAddress <= 0;
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oRAMWriteAddress <= 0;
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oEnableWBM <= 0;
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oEnableWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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oNodeReadDone <= 0;
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oNodeReadDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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rFFEnNumVertices <= 0;
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rFFEnNumVertices <= 0;
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rFFEnDataOffset <= 0;
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rFFEnDataOffset <= 0;
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rFFEnBrotherAddress <= 0;
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rFFEnBrotherAddress <= 0;
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rFFEnParentsBroAddr <= 0;
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rFFEnParentsBroAddr <= 0;
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|
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NextState <= `TNF_IDLE;
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NextState <= `TNF_IDLE;
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end
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end
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//------------------------------------
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//------------------------------------
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`TNF_IDLE:
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`TNF_IDLE:
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begin
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begin
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oRAMWriteAddress <= 0;
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oRAMWriteAddress <= 0;
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oEnableWBM <= 0;
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oEnableWBM <= 0;
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oSetAddressWBM <= 0;
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oSetAddressWBM <= 0;
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oNodeReadDone <= 0;
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oNodeReadDone <= 0;
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oRAMWriteEnable <= 0;
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oRAMWriteEnable <= 0;
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rFFEnNumVertices <= 0;
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rFFEnNumVertices <= 0;
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rFFEnDataOffset <= 0;
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rFFEnDataOffset <= 0;
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rFFEnBrotherAddress <= 0;
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rFFEnBrotherAddress <= 0;
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rFFEnParentsBroAddr <= 0;
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rFFEnParentsBroAddr <= 0;
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|
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if (iTrigger)
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if (iTrigger)
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NextState <= `TNF_REQUEST_AABBMIN;
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NextState <= `TNF_REQUEST_AABBMIN;
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else
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else
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NextState <= `TNF_IDLE;
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NextState <= `TNF_IDLE;
|
|
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end
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end
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//------------------------------------
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//------------------------------------
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/*
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/*
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Here tell WBM to read from address iInitialAddress by seeting
|
Here tell WBM to read from address iInitialAddress by seeting
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oSetAddressWBM = 1.
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oSetAddressWBM = 1.
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By setting oRAMWriteEnable = 1, we are also telling WBM to
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By setting oRAMWriteEnable = 1, we are also telling WBM to
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store the the value in iInitialAddress, iInitialAddress+1,
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store the the value in iInitialAddress, iInitialAddress+1,
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and iInitialAddress+2 into RAM, so the WBMAddress is going
|
and iInitialAddress+2 into RAM, so the WBMAddress is going
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to increment by 3.
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to increment by 3.
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*/
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*/
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`TNF_REQUEST_AABBMIN:
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`TNF_REQUEST_AABBMIN:
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begin
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begin
|
oRAMWriteAddress <= `CREG_AABBMIN;
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oRAMWriteAddress <= `CREG_AABBMIN;
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oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
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oSetAddressWBM <= 1; //*
|
oSetAddressWBM <= 1; //*
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oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 1; //*
|
oRAMWriteEnable <= 1; //*
|
rFFEnBrotherAddress <= 0;
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rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_WAIT_FOR_AABBMIN;
|
NextState <= `TNF_WAIT_FOR_AABBMIN;
|
|
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_FOR_AABBMIN:
|
`TNF_WAIT_FOR_AABBMIN:
|
begin
|
begin
|
oRAMWriteAddress <= `CREG_AABBMIN;
|
oRAMWriteAddress <= `CREG_AABBMIN;
|
oEnableWBM <= 1;
|
oEnableWBM <= 1;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 1;//*
|
oRAMWriteEnable <= 1;//*
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_REQUEST_AABBMAX;
|
NextState <= `TNF_REQUEST_AABBMAX;
|
else
|
else
|
NextState <= `TNF_WAIT_FOR_AABBMIN;
|
NextState <= `TNF_WAIT_FOR_AABBMIN;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_REQUEST_AABBMAX:
|
`TNF_REQUEST_AABBMAX:
|
begin
|
begin
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oEnableWBM <= 1;
|
oEnableWBM <= 1;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 1;//*
|
oRAMWriteEnable <= 1;//*
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_WAIT_FOR_AABBMAX;
|
NextState <= `TNF_WAIT_FOR_AABBMAX;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_FOR_AABBMAX:
|
`TNF_WAIT_FOR_AABBMAX:
|
begin
|
begin
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oEnableWBM <= 1;
|
oEnableWBM <= 1;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 1;//*
|
oRAMWriteEnable <= 1;//*
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
|
NextState <= `TNF_REQUEST_NUMBER_OF_TRIANGLES;
|
else
|
else
|
NextState <= `TNF_WAIT_FOR_AABBMAX;
|
NextState <= `TNF_WAIT_FOR_AABBMAX;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_REQUEST_NUMBER_OF_TRIANGLES:
|
`TNF_REQUEST_NUMBER_OF_TRIANGLES:
|
begin
|
begin
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oRAMWriteAddress <= `CREG_AABBMAX;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0; //* to give more time to write
|
oRAMWriteEnable <= 0; //* to give more time to write
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
|
NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
|
`TNF_WAIT_FOR_NUMBER_OF_TRIANGLES:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1;
|
oEnableWBM <= 1;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
|
NextState <= `TNF_LATCH_NUMBER_OF_TRIANGLES;
|
else
|
else
|
NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
|
NextState <= `TNF_WAIT_FOR_NUMBER_OF_TRIANGLES;
|
|
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_LATCH_NUMBER_OF_TRIANGLES:
|
`TNF_LATCH_NUMBER_OF_TRIANGLES:
|
begin
|
begin
|
|
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0; //*
|
oNodeReadDone <= 0; //*
|
rFFEnNumVertices <= 1;
|
rFFEnNumVertices <= 1;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
|
|
NextState <= `TNF_REQUEST_DATA_OFFSET;
|
NextState <= `TNF_REQUEST_DATA_OFFSET;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_REQUEST_DATA_OFFSET:
|
`TNF_REQUEST_DATA_OFFSET:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
|
NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_FOR_DATA_OFFSET:
|
`TNF_WAIT_FOR_DATA_OFFSET:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_LATCH_DATA_OFFSET;
|
NextState <= `TNF_LATCH_DATA_OFFSET;
|
else
|
else
|
NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
|
NextState <= `TNF_WAIT_FOR_DATA_OFFSET;
|
|
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_LATCH_DATA_OFFSET:
|
`TNF_LATCH_DATA_OFFSET:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 1; //*
|
rFFEnDataOffset <= 1; //*
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
|
NextState <= `TNF_REQUEST_NODE_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_REQUEST_NODE_BROTHER_ADDRESS:
|
`TNF_REQUEST_NODE_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 1;
|
rFFEnDataOffset <= 1;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
|
NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
|
`TNF_WAIT_FOR_NODE_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
|
NextState <= `TNF_LACTH_NODE_BROTHER_ADDRESS;
|
else
|
else
|
NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
|
NextState <= `TNF_WAIT_FOR_NODE_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_LACTH_NODE_BROTHER_ADDRESS:
|
`TNF_LACTH_NODE_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 1; //*
|
rFFEnBrotherAddress <= 1; //*
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
|
NextState <= `TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
|
`TNF_REQUEST_NODE_PARENT_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1; //*
|
oEnableWBM <= 1; //*
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
//rLastAddress <= 1;
|
//rLastAddress <= 1;
|
|
|
NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
|
NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
|
`TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 1;
|
oEnableWBM <= 1;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iDataAvailable )
|
if ( iDataAvailable )
|
NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
|
NextState <= `TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS;
|
else
|
else
|
NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
|
NextState <= `TNF_WAIT_NODE_PARENT_BROTHER_ADDRESS;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
|
`TNF_LATCH_NODE_PARENT_BROTHER_ADDRESS:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 1;
|
rFFEnParentsBroAddr <= 1;
|
|
|
NextState <= `TNF_WAIT_NODE_READ_ACK;
|
NextState <= `TNF_WAIT_NODE_READ_ACK;
|
|
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
`TNF_WAIT_NODE_READ_ACK:
|
`TNF_WAIT_NODE_READ_ACK:
|
begin
|
begin
|
|
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 1; //*
|
oNodeReadDone <= 1; //*
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
if ( iTrigger == 0 )
|
if ( iTrigger == 0 )
|
NextState <= `TNF_IDLE;
|
NextState <= `TNF_IDLE;
|
else
|
else
|
NextState <= `TNF_WAIT_NODE_READ_ACK;
|
NextState <= `TNF_WAIT_NODE_READ_ACK;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
default:
|
default:
|
begin
|
begin
|
oRAMWriteAddress <= 0;
|
oRAMWriteAddress <= 0;
|
oEnableWBM <= 0;
|
oEnableWBM <= 0;
|
oSetAddressWBM <= 0;
|
oSetAddressWBM <= 0;
|
oNodeReadDone <= 0;
|
oNodeReadDone <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnNumVertices <= 0;
|
rFFEnDataOffset <= 0;
|
rFFEnDataOffset <= 0;
|
oRAMWriteEnable <= 0;
|
oRAMWriteEnable <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnBrotherAddress <= 0;
|
rFFEnParentsBroAddr <= 0;
|
rFFEnParentsBroAddr <= 0;
|
|
|
NextState <= `TNF_IDLE;
|
NextState <= `TNF_IDLE;
|
end
|
end
|
//------------------------------------
|
//------------------------------------
|
endcase
|
endcase
|
end //always
|
end //always
|
endmodule
|
endmodule
|
|
|
