`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "aDefinitions.v"
|
`include "aDefinitions.v"
|
/**********************************************************************************
|
/**********************************************************************************
|
Theia, Ray Cast Programable graphic Processing Unit.
|
Theia, Ray Cast Programable graphic Processing Unit.
|
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
|
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
|
|
|
This program is free software; you can redistribute it and/or
|
This program is free software; you can redistribute it and/or
|
modify it under the terms of the GNU General Public License
|
modify it under the terms of the GNU General Public License
|
as published by the Free Software Foundation; either version 2
|
as published by the Free Software Foundation; either version 2
|
of the License, or (at your option) any later version.
|
of the License, or (at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
|
***********************************************************************************/
|
***********************************************************************************/
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
//Dual port RAM.
|
//Dual port RAM.
|
//Each Row has 3* 32 bit entries (x,y and Z)
|
//Each Row has 3* 32 bit entries (x,y and Z)
|
|
|
module RAM_DATA
|
module RAM_DATA
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire iWriteEnable,
|
input wire iWriteEnable,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress0,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress0,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress1,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress1,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iWriteAddress,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iWriteAddress,
|
input wire[`DATA_ROW_WIDTH-1:0] iDataIn,
|
input wire[`DATA_ROW_WIDTH-1:0] iDataIn,
|
output reg [`DATA_ROW_WIDTH-1:0] oDataOut0,
|
output reg [`DATA_ROW_WIDTH-1:0] oDataOut0,
|
output reg [`DATA_ROW_WIDTH-1:0] oDataOut1
|
output reg [`DATA_ROW_WIDTH-1:0] oDataOut1
|
);
|
);
|
|
|
reg [`DATA_ROW_WIDTH-1:0] Ram [128:0];
|
reg [`DATA_ROW_WIDTH-1:0] Ram [128:0];
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
|
|
if (iWriteEnable)
|
if (iWriteEnable)
|
Ram[iWriteAddress] <= iDataIn;
|
Ram[iWriteAddress] <= iDataIn;
|
|
|
|
|
oDataOut0 <= Ram[iReadAddress0];
|
oDataOut0 <= Ram[iReadAddress0];
|
oDataOut1 <= Ram[iReadAddress1];
|
oDataOut1 <= Ram[iReadAddress1];
|
|
|
end
|
end
|
endmodule
|
endmodule
|
//--------------------------------------------------------
|
//--------------------------------------------------------
|
//Single port RAM.
|
//Single port RAM.
|
module RAM_INST
|
module RAM_INST
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire iWriteEnable,
|
input wire iWriteEnable,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iReadAddress,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iWriteAddress,
|
input wire[`DATA_ADDRESS_WIDTH-1:0] iWriteAddress,
|
input wire[`INSTRUCTION_WIDTH-1:0] iDataIn,
|
input wire[`INSTRUCTION_WIDTH-1:0] iDataIn,
|
output reg [`INSTRUCTION_WIDTH-1:0] oDataOut
|
output reg [`INSTRUCTION_WIDTH-1:0] oDataOut
|
|
|
);
|
);
|
|
|
reg [`INSTRUCTION_WIDTH-1:0] Ram [128:0];
|
reg [`INSTRUCTION_WIDTH-1:0] Ram [128:0];
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
|
|
if (iWriteEnable)
|
if (iWriteEnable)
|
Ram[iWriteAddress] <= iDataIn;
|
Ram[iWriteAddress] <= iDataIn;
|
|
|
oDataOut <= Ram[iReadAddress];
|
oDataOut <= Ram[iReadAddress];
|
|
|
|
|
end
|
end
|
endmodule
|
endmodule
|
|
|
