`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`include "aDefinitions.v"
|
`include "aDefinitions.v"
|
/**********************************************************************************
|
/**********************************************************************************
|
Theia, Ray Cast Programable graphic Processing Unit.
|
Theia, Ray Cast Programable graphic Processing Unit.
|
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
|
Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
|
|
|
This program is free software; you can redistribute it and/or
|
This program is free software; you can redistribute it and/or
|
modify it under the terms of the GNU General Public License
|
modify it under the terms of the GNU General Public License
|
as published by the Free Software Foundation; either version 2
|
as published by the Free Software Foundation; either version 2
|
of the License, or (at your option) any later version.
|
of the License, or (at your option) any later version.
|
|
|
This program is distributed in the hope that it will be useful,
|
This program is distributed in the hope that it will be useful,
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
GNU General Public License for more details.
|
GNU General Public License for more details.
|
|
|
You should have received a copy of the GNU General Public License
|
You should have received a copy of the GNU General Public License
|
along with this program; if not, write to the Free Software
|
along with this program; if not, write to the Free Software
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
|
|
***********************************************************************************/
|
***********************************************************************************/
|
//------------------------------------------------
|
//------------------------------------------------
|
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
|
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Clear,
|
input wire Clear,
|
input wire [SIZE-1:0] D,
|
input wire [SIZE-1:0] D,
|
output reg [SIZE-1:0] Q
|
output reg [SIZE-1:0] Q
|
);
|
);
|
|
|
always @(posedge Clock or posedge Clear)
|
always @(posedge Clock or posedge Clear)
|
begin
|
begin
|
if (Clear)
|
if (Clear)
|
Q = 0;
|
Q = 0;
|
else
|
else
|
Q = D;
|
Q = D;
|
end
|
end
|
endmodule
|
endmodule
|
//----------------------------------------------------
|
//----------------------------------------------------
|
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
|
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire Enable,
|
input wire Enable,
|
input wire [SIZE-1:0] D,
|
input wire [SIZE-1:0] D,
|
output reg [SIZE-1:0] Q
|
output reg [SIZE-1:0] Q
|
);
|
);
|
|
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
begin
|
begin
|
if ( Reset )
|
if ( Reset )
|
Q <= `WIDTH'b0;
|
Q <= `WIDTH'b0;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
Q <= D;
|
Q <= D;
|
end
|
end
|
|
|
end//always
|
end//always
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
|
module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
|
(
|
(
|
input wire Clock, Reset,
|
input wire Clock, Reset,
|
input wire [SIZE-1:0] Initial,
|
input wire [SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output reg [SIZE-1:0] Q
|
output reg [SIZE-1:0] Q
|
);
|
);
|
|
|
|
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Q = Initial;
|
Q = Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
Q = Q + 1;
|
Q = Q + 1;
|
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [1:0] Sel,
|
input wire [1:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,I4,
|
input wire [SIZE-1:0]I1, I2, I3,I4,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
2'b00: O1 = I1;
|
2'b00: O1 = I1;
|
2'b01: O1 = I2;
|
2'b01: O1 = I2;
|
2'b10: O1 = I3;
|
2'b10: O1 = I3;
|
2'b11: O1 = I4;
|
2'b11: O1 = I4;
|
default: O1 = SIZE-1'b0;
|
default: O1 = SIZE-1'b0;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//--------
|
//--------
|
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
|
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
begin
|
begin
|
if (tmp[SIZE-1])
|
if (tmp[SIZE-1])
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [2:0] Sel,
|
input wire [2:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
3'b001: O1 = I1;
|
3'b001: O1 = I1;
|
3'b010: O1 = I2;
|
3'b010: O1 = I2;
|
3'b100: O1 = I3;
|
3'b100: O1 = I3;
|
default: O1 = SIZE-1'b0;
|
default: O1 = SIZE-1'b0;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
//------------------------------------------------
|
//------------------------------------------------
|
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
|
( input wire Clock,
|
( input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire[SIZE-1:0] Initial,
|
input wire[SIZE-1:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire[SIZE-1:0] O
|
output wire[SIZE-1:0] O
|
);
|
);
|
|
|
reg [SIZE-1:0] tmp;
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
always @(posedge Clock)
|
always @(posedge Clock)
|
begin
|
begin
|
if (Reset || tmp[SIZE-1])
|
if (Reset || tmp[SIZE-1])
|
tmp <= Initial;
|
tmp <= Initial;
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
tmp <= tmp << 1;
|
tmp <= tmp << 1;
|
end
|
end
|
end
|
end
|
|
|
|
|
assign O = tmp;
|
assign O = tmp;
|
endmodule
|
endmodule
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
/*
|
/*
|
Sorry forgot how this flop is called.
|
Sorry forgot how this flop is called.
|
Any way Truth table is this
|
Any way Truth table is this
|
|
|
Q S Q_next R
|
Q S Q_next R
|
0 0 0 0
|
0 0 0 0
|
0 1 1 0
|
0 1 1 0
|
1 0 1 0
|
1 0 1 0
|
1 1 1 0
|
1 1 1 0
|
X X 0 1
|
X X 0 1
|
|
|
The idea is that it toggles from 0 to 1 when S = 1, but if it
|
The idea is that it toggles from 0 to 1 when S = 1, but if it
|
gets another S = 1, it keeps the output to 1.
|
gets another S = 1, it keeps the output to 1.
|
*/
|
*/
|
module FFToggleOnce_1Bit
|
module FFToggleOnce_1Bit
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire Enable,
|
input wire Enable,
|
input wire S,
|
input wire S,
|
output reg Q
|
output reg Q
|
|
|
);
|
);
|
|
|
|
|
reg Q_next;
|
reg Q_next;
|
|
|
always @ (negedge Clock)
|
always @ (negedge Clock)
|
begin
|
begin
|
Q <= Q_next;
|
Q <= Q_next;
|
end
|
end
|
|
|
always @ ( posedge Clock )
|
always @ ( posedge Clock )
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Q_next <= 0;
|
Q_next <= 0;
|
else if (Enable)
|
else if (Enable)
|
Q_next <= (S && !Q) || Q;
|
Q_next <= (S && !Q) || Q;
|
else
|
else
|
Q_next <= Q;
|
Q_next <= Q;
|
end
|
end
|
endmodule
|
endmodule
|
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//************************OLD MODS***************************//
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
|
|
/*
|
/*
|
module UpCounterXXX_16
|
module UpCounterXXX_16
|
(
|
(
|
input wire Clock, Reset,
|
input wire Clock, Reset,
|
input wire [15:0] Initial,
|
input wire [15:0] Initial,
|
output reg [15:0] Q
|
output reg [15:0] Q
|
);
|
);
|
|
|
|
|
always @(posedge Clock )
|
always @(posedge Clock )
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Q = Initial;
|
Q = Initial;
|
else
|
else
|
Q = Q + 1'b1;
|
Q = Q + 1'b1;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
*/
|
*/
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
module UpCounter_16E
|
module UpCounter_16E
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire [15:0] Initial,
|
input wire [15:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire [15:0] Q
|
output wire [15:0] Q
|
);
|
);
|
reg [15:0] Temp;
|
reg [15:0] Temp;
|
|
|
|
|
always @(posedge Clock or posedge Reset)
|
always @(posedge Clock or posedge Reset)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Temp = Initial;
|
Temp = Initial;
|
else
|
else
|
if (Enable)
|
if (Enable)
|
Temp = Temp + 1'b1;
|
Temp = Temp + 1'b1;
|
end
|
end
|
assign Q = Temp;
|
assign Q = Temp;
|
|
|
endmodule
|
endmodule
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
module UpCounter_32
|
module UpCounter_32
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire [31:0] Initial,
|
input wire [31:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire [31:0] Q
|
output wire [31:0] Q
|
);
|
);
|
reg [31:0] Temp;
|
reg [31:0] Temp;
|
|
|
|
|
always @(posedge Clock or posedge Reset)
|
always @(posedge Clock or posedge Reset)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Temp = Initial;
|
Temp = Initial;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (Enable)
|
if (Enable)
|
begin
|
begin
|
Temp = Temp + 1'b1;
|
Temp = Temp + 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
assign Q = Temp;
|
assign Q = Temp;
|
|
|
endmodule
|
endmodule
|
//-----------------------------------------------------------
|
//-----------------------------------------------------------
|
module UpCounter_3
|
module UpCounter_3
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Reset,
|
input wire Reset,
|
input wire [2:0] Initial,
|
input wire [2:0] Initial,
|
input wire Enable,
|
input wire Enable,
|
output wire [2:0] Q
|
output wire [2:0] Q
|
);
|
);
|
reg [2:0] Temp;
|
reg [2:0] Temp;
|
|
|
|
|
always @(posedge Clock or posedge Reset)
|
always @(posedge Clock or posedge Reset)
|
begin
|
begin
|
if (Reset)
|
if (Reset)
|
Temp = Initial;
|
Temp = Initial;
|
else
|
else
|
if (Enable)
|
if (Enable)
|
Temp = Temp + 3'b1;
|
Temp = Temp + 3'b1;
|
end
|
end
|
assign Q = Temp;
|
assign Q = Temp;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
module FFD32_POSEDGE
|
module FFD32_POSEDGE
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire[31:0] D,
|
input wire[31:0] D,
|
output reg[31:0] Q
|
output reg[31:0] Q
|
);
|
);
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
Q <= D;
|
Q <= D;
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
/*
|
/*
|
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
|
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Clear,
|
input wire Clear,
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
);
|
);
|
|
|
always @(posedge Clock or posedge Clear)
|
always @(posedge Clock or posedge Clear)
|
begin
|
begin
|
if (Clear)
|
if (Clear)
|
Q = `INSTRUCTION_OP_LENGTH'b0;
|
Q = `INSTRUCTION_OP_LENGTH'b0;
|
else
|
else
|
Q = D;
|
Q = D;
|
end
|
end
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
module FF32_POSEDGE_SYNCRONOUS_RESET
|
module FF32_POSEDGE_SYNCRONOUS_RESET
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Clear,
|
input wire Clear,
|
input wire[31:0] D,
|
input wire[31:0] D,
|
output reg[31:0] Q
|
output reg[31:0] Q
|
);
|
);
|
|
|
always @(posedge Clock or posedge Clear)
|
always @(posedge Clock or posedge Clear)
|
begin
|
begin
|
if (Clear)
|
if (Clear)
|
Q = 32'b0;
|
Q = 32'b0;
|
else
|
else
|
Q = D;
|
Q = D;
|
end
|
end
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
module FF16_POSEDGE_SYNCRONOUS_RESET
|
module FF16_POSEDGE_SYNCRONOUS_RESET
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire Clear,
|
input wire Clear,
|
input wire[15:0] D,
|
input wire[15:0] D,
|
output reg[15:0] Q
|
output reg[15:0] Q
|
);
|
);
|
|
|
always @(posedge Clock or posedge Clear)
|
always @(posedge Clock or posedge Clear)
|
begin
|
begin
|
if (Clear)
|
if (Clear)
|
Q = 16'b0;
|
Q = 16'b0;
|
else
|
else
|
Q = D;
|
Q = D;
|
end
|
end
|
endmodule
|
endmodule
|
*/
|
*/
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_96bits_2SEL
|
module MUXFULLPARALELL_96bits_2SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire [95:0]I1, I2,
|
input wire [95:0]I1, I2,
|
output reg [95:0] O1
|
output reg [95:0] O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
1'b0: O1 = I1;
|
1'b0: O1 = I1;
|
1'b1: O1 = I2;
|
1'b1: O1 = I2;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
|
|
module MUXFULLPARALELL_16bits_2SEL_X
|
module MUXFULLPARALELL_16bits_2SEL_X
|
(
|
(
|
input wire [1:0] Sel,
|
input wire [1:0] Sel,
|
input wire [15:0]I1, I2, I3,
|
input wire [15:0]I1, I2, I3,
|
output reg [15:0] O1
|
output reg [15:0] O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
2'b00: O1 = I1;
|
2'b00: O1 = I1;
|
2'b01: O1 = I2;
|
2'b01: O1 = I2;
|
2'b10: O1 = I3;
|
2'b10: O1 = I3;
|
default: O1 = 16'b0;
|
default: O1 = 16'b0;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_16bits_2SEL
|
module MUXFULLPARALELL_16bits_2SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire [15:0]I1, I2,
|
input wire [15:0]I1, I2,
|
output reg [15:0] O1
|
output reg [15:0] O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
1'b0: O1 = I1;
|
1'b0: O1 = I1;
|
1'b1: O1 = I2;
|
1'b1: O1 = I2;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
/*
|
/*
|
module MUXFULLPARALELL_1Bit_1SEL
|
module MUXFULLPARALELL_1Bit_1SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire I1, I2,
|
input wire I1, I2,
|
output reg O1
|
output reg O1
|
);
|
);
|
|
|
|
|
|
|
always @( * )
|
always @( * )
|
|
|
begin
|
begin
|
|
|
case (Sel)
|
case (Sel)
|
|
|
1'b0: O1 = I1;
|
1'b0: O1 = I1;
|
1'b1: O1 = I2;
|
1'b1: O1 = I2;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
*/
|
*/
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
/*
|
/*
|
module FFD_OPCODE_POSEDGE
|
module FFD_OPCODE_POSEDGE
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
);
|
);
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
Q <= D;
|
Q <= D;
|
|
|
endmodule
|
endmodule
|
*/
|
*/
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
/*
|
/*
|
module FFD16_POSEDGE
|
module FFD16_POSEDGE
|
(
|
(
|
input wire Clock,
|
input wire Clock,
|
input wire[15:0] D,
|
input wire[15:0] D,
|
output reg[15:0] Q
|
output reg[15:0] Q
|
);
|
);
|
|
|
always @ (posedge Clock)
|
always @ (posedge Clock)
|
Q <= D;
|
Q <= D;
|
|
|
endmodule
|
endmodule
|
*/
|
*/
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
module FFT1
|
module FFT1
|
(
|
(
|
input wire D,
|
input wire D,
|
input wire Clock,
|
input wire Clock,
|
input wire Reset ,
|
input wire Reset ,
|
output reg Q
|
output reg Q
|
);
|
);
|
|
|
always @ ( posedge Clock or posedge Reset )
|
always @ ( posedge Clock or posedge Reset )
|
begin
|
begin
|
|
|
if (Reset)
|
if (Reset)
|
begin
|
begin
|
Q <= 1'b0;
|
Q <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if (D)
|
if (D)
|
Q <= ! Q;
|
Q <= ! Q;
|
end
|
end
|
|
|
end//always
|
end//always
|
|
|
endmodule
|
endmodule
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
