`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/**********************************************************************************
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/**********************************************************************************
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Description:
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Description:
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This is the instruction fetch unit.
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This is the instruction fetch unit.
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It gets the next instruction from the IMEM module at the MEM unit.
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It gets the next instruction from the IMEM module at the MEM unit.
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It increments the instruction pointer (IP) in such a way that EXE has always
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It increments the instruction pointer (IP) in such a way that EXE has always
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one instruction per clock cycle (best pipeline performance). In order to achieve this,
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one instruction per clock cycle (best pipeline performance). In order to achieve this,
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IFU has 2 instruction pointers, so that in case of 'branch' instructions,
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IFU has 2 instruction pointers, so that in case of 'branch' instructions,
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two instructions pointer are generated and two different instructions are simultaneously
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two instructions pointer are generated and two different instructions are simultaneously
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fetched from IMEM: the branch-taken and branch-not-taken instructions, so that once the
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fetched from IMEM: the branch-taken and branch-not-taken instructions, so that once the
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branch outcome is calculted in EXE, both possible outcomes are already pre-fetched.
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branch outcome is calculted in EXE, both possible outcomes are already pre-fetched.
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**********************************************************************************/
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**********************************************************************************/
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module InstructionFetch
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module InstructionFetch
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iTrigger,
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input wire iTrigger,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress,
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input wire[`ROM_ADDRESS_WIDTH-1:0] iInitialCodeAddress,
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction1, //Branch not taken instruction
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction1, //Branch not taken instruction
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction2, //Branch taken instruction
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input wire[`INSTRUCTION_WIDTH-1:0] iInstruction2, //Branch taken instruction
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input wire iBranchTaken,
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input wire iBranchTaken,
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output wire oInstructionAvalable,
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output wire oInstructionAvalable,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP2, //calcule both decide later
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output wire [`ROM_ADDRESS_WIDTH-1:0] oIP2, //calcule both decide later
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output wire[`INSTRUCTION_WIDTH-1:0] oCurrentInstruction,
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output wire[`INSTRUCTION_WIDTH-1:0] oCurrentInstruction,
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input wire iEXEDone,
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input wire iEXEDone,
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output wire oMicroCodeReturnValue,
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output wire oMicroCodeReturnValue,
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output wire oExecutionDone
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output wire oExecutionDone
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);
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);
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`define INSTRUCTION_OPCODE oCurrentInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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`define INSTRUCTION_OPCODE oCurrentInstruction[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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//iInstruction1[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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//iInstruction1[`INSTRUCTION_WIDTH-1:`INSTRUCTION_WIDTH-`INSTRUCTION_OP_LENGTH]
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assign oMicroCodeReturnValue = oCurrentInstruction[0];
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assign oMicroCodeReturnValue = oCurrentInstruction[0];
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assign oIP2 = oCurrentInstruction[47:32];//iInstruction1[47:32];
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assign oIP2 = oCurrentInstruction[47:32];//iInstruction1[47:32];
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wire wTriggerDelay1,wTriggerDelay2,wIncrementIP_Delay1,wIncrementIP_Delay2,
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wire wTriggerDelay1,wTriggerDelay2,wIncrementIP_Delay1,wIncrementIP_Delay2,
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wLastInst_Delay1,wLastInst_Delay2;
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wLastInst_Delay1,wLastInst_Delay2;
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wire wIncrementIP,wLastInstruction;
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wire wIncrementIP,wLastInstruction;
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assign wLastInstruction = (`INSTRUCTION_OPCODE == `RETURN);
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assign wLastInstruction = (`INSTRUCTION_OPCODE == `RETURN);
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//Increment IP 2 cycles after trigger or everytime EXE is done, but stop if we get to the RETURN
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//Increment IP 2 cycles after trigger or everytime EXE is done, but stop if we get to the RETURN
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assign wIncrementIP = wTriggerDelay2 | (iEXEDone & ~wLastInstruction);
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assign wIncrementIP = wTriggerDelay2 | (iEXEDone & ~wLastInstruction);
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//It takes 1 clock cycle to read the instruction back from IMEM
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//It takes 1 clock cycle to read the instruction back from IMEM
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assign oInstructionAvalable = wTriggerDelay2 | (iEXEDone & ~wLastInst_Delay2);
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assign oInstructionAvalable = wTriggerDelay2 | (iEXEDone & ~wLastInst_Delay2);
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//Once we reach the last instruction, wait until EXE says he is done, then assert oExecutionDone
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//Once we reach the last instruction, wait until EXE says he is done, then assert oExecutionDone
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assign oExecutionDone = (wLastInstruction & iEXEDone);
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assign oExecutionDone = (wLastInstruction & iEXEDone);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(1'b1),
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.Enable(1'b1),
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.D( iTrigger ),
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.D( iTrigger ),
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.Q( wTriggerDelay1 )
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.Q( wTriggerDelay1 )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD3
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(1'b1),
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.Enable(1'b1),
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.D( wTriggerDelay1 ),
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.D( wTriggerDelay1 ),
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.Q( wTriggerDelay2 )
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.Q( wTriggerDelay2 )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD4
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(wLastInstruction),
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.Enable(wLastInstruction),
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.D( oInstructionAvalable ),
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.D( oInstructionAvalable ),
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.Q( wLastInst_Delay1 )
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.Q( wLastInst_Delay1 )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD5
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(1'b1),//wLastInstruction),
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.Enable(1'b1),//wLastInstruction),
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.D( wLastInst_Delay1 ),
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.D( wLastInst_Delay1 ),
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.Q( wLastInst_Delay2 )
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.Q( wLastInst_Delay2 )
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);
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);
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wire [`ROM_ADDRESS_WIDTH-1:0] oIP2_Next;
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wire [`ROM_ADDRESS_WIDTH-1:0] oIP2_Next;
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/*
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/*
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In case the branch is taken:
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In case the branch is taken:
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We point current instruction into the iInstruction2 (branch-taken) instruction
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We point current instruction into the iInstruction2 (branch-taken) instruction
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that corresponds to oIP2.
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that corresponds to oIP2.
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Then, in the next clock cycle we should use the oIP2 incremented by one,
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Then, in the next clock cycle we should use the oIP2 incremented by one,
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so we need to load UPCOUNTER_POSEDGE with oIP2+1
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so we need to load UPCOUNTER_POSEDGE with oIP2+1
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*/
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*/
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//If the branch was taken, then use the pre-fetched instruction (iInstruction2)
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//If the branch was taken, then use the pre-fetched instruction (iInstruction2)
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wire[`INSTRUCTION_WIDTH-1:0] wCurrentInstruction_Delay1,wCurrentInstruction_BranchTaken;
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wire[`INSTRUCTION_WIDTH-1:0] wCurrentInstruction_Delay1,wCurrentInstruction_BranchTaken;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDX
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDX
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(iBranchTaken),
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.Enable(iBranchTaken),
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.D( oCurrentInstruction ),
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.D( oCurrentInstruction ),
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.Q( wCurrentInstruction_Delay1 )
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.Q( wCurrentInstruction_Delay1 )
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);
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);
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wire wBranchTaken_Delay1;
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wire wBranchTaken_Delay1;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDY
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDY
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable(1'b1),
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.Enable(1'b1),
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.D( iBranchTaken ),
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.D( iBranchTaken ),
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.Q( wBranchTaken_Delay1 )
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.Q( wBranchTaken_Delay1 )
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);
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);
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assign wCurrentInstruction_BranchTaken = (iBranchTaken ) ? iInstruction2 : iInstruction1;
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assign wCurrentInstruction_BranchTaken = (iBranchTaken ) ? iInstruction2 : iInstruction1;
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assign oCurrentInstruction = (wBranchTaken_Delay1) ?
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assign oCurrentInstruction = (wBranchTaken_Delay1) ?
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wCurrentInstruction_Delay1 : wCurrentInstruction_BranchTaken;
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wCurrentInstruction_Delay1 : wCurrentInstruction_BranchTaken;
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INCREMENT # (`ROM_ADDRESS_WIDTH) INC1
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INCREMENT # (`ROM_ADDRESS_WIDTH) INC1
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.A( oIP2 ),
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.A( oIP2 ),
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.R( oIP2_Next )
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.R( oIP2_Next )
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);
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);
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wire[`ROM_ADDRESS_WIDTH-1:0] wIPEntryPoint;
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wire[`ROM_ADDRESS_WIDTH-1:0] wIPEntryPoint;
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assign wIPEntryPoint = (iBranchTaken) ? oIP2_Next : iInitialCodeAddress;
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assign wIPEntryPoint = (iBranchTaken) ? oIP2_Next : iInitialCodeAddress;
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UPCOUNTER_POSEDGE # (`ROM_ADDRESS_WIDTH) InstructionPointer
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UPCOUNTER_POSEDGE # (`ROM_ADDRESS_WIDTH) InstructionPointer
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset(iTrigger | iBranchTaken),
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.Reset(iTrigger | iBranchTaken),
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.Enable(wIncrementIP & ~iBranchTaken ),
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.Enable(wIncrementIP & ~iBranchTaken ),
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.Initial( wIPEntryPoint ),
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.Initial( wIPEntryPoint ),
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.Q(oIP)
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.Q(oIP)
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);
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);
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endmodule
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endmodule
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