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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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***********************************************************************************/
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/**
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/**
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The Wish Bone bus has a 32 bit words.
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The Wish Bone bus has a 32 bit words.
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However our internal bus is 96 bits (32 * 3) bits wide
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However our internal bus is 96 bits (32 * 3) bits wide
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for Data or 64 bits wide for Instructions (Hardvard Architecture).
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for Data or 64 bits wide for Instructions (Hardvard Architecture).
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If the iStore signal is one, WBM2MEMUnit provides a means to
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If the iStore signal is one, WBM2MEMUnit provides a means to
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store 2 or 3 incomming 32 bits frames into temporary Flip-Flops,
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store 2 or 3 incomming 32 bits frames into temporary Flip-Flops,
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and then store the 96 or 64 bit value into a specified location
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and then store the 96 or 64 bit value into a specified location
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in the internal Instruction or Data Memory.
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in the internal Instruction or Data Memory.
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If the iStore signal is zero, WBMinputFifo passes the
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If the iStore signal is zero, WBMinputFifo passes the
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32 bit value comming from the WB bus, directly through the oData
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32 bit value comming from the WB bus, directly through the oData
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pin without storing it.
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pin without storing it.
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*/
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*/
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module WBM2MEMUnit
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module WBM2MEMUnit
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iEnable,
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input wire iEnable,
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input wire iStore,
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input wire iStore,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iAdr_DataWriteBack,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iAdr_DataWriteBack,
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input wire iWBMDataAvailable,
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input wire iWBMDataAvailable,
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input wire iWriteBack_Set,
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input wire iWriteBack_Set,
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//input wire[`WIDTH-1:0] iWBMInitialAddress,
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//input wire[`WIDTH-1:0] iWBMInitialAddress,
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//input wire iSetWBMInitialAddress,
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//input wire iSetWBMInitialAddress,
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input wire [`WIDTH-1:0] iWBMData, //Comes from WBM
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input wire [`WIDTH-1:0] iWBMData, //Comes from WBM
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output wire[`WIDTH-1:0] oData, //Goes back to geo
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output wire[`WIDTH-1:0] oData, //Goes back to geo
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output wire oEnableWBM,
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output wire oEnableWBM,
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//output wire[`WIDTH-1:0] oAddressWBM,
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//output wire[`WIDTH-1:0] oAddressWBM,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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output wire[`DATA_ADDRESS_WIDTH-1:0] oDataWriteAddress,
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inout wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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inout wire [`DATA_ROW_WIDTH-1:0] oDataBus,
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output wire oDataWriteEnable,
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output wire oDataWriteEnable,
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output wire oDone
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output wire oDone
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);
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);
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wire [`WIDTH-1:0] wVx;
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wire [`WIDTH-1:0] wVx;
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wire [`WIDTH-1:0] wVy;
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wire [`WIDTH-1:0] wVy;
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wire [`WIDTH-1:0] wVz;
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wire [`WIDTH-1:0] wVz;
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wire wDelayAfterWriteEnable;
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wire wDelayAfterWriteEnable;
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//assign oDataWriteAddress = iAdr_DataWriteBack;
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//assign oDataWriteAddress = iAdr_DataWriteBack;
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wire CounterClock;
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wire CounterClock;
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assign CounterClock = wDelayAfterWriteEnable | iWriteBack_Set;
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assign CounterClock = wDelayAfterWriteEnable | iWriteBack_Set;
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UPCOUNTER_POSEDGE # (`DATA_ADDRESS_WIDTH) UP1
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UPCOUNTER_POSEDGE # (`DATA_ADDRESS_WIDTH) UP1
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(
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(
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.Clock(Clock),
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.Clock(Clock),
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.Reset(iWriteBack_Set | Reset ),
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.Reset(iWriteBack_Set | Reset ),
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.Enable(CounterClock),
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.Enable(CounterClock),
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.Initial(iAdr_DataWriteBack),
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.Initial(iAdr_DataWriteBack),
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.Q(oDataWriteAddress)
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.Q(oDataWriteAddress)
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);
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);
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wire[3:0] wSelXYZ;
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wire[3:0] wSelXYZ;
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//Every time WBM says is done, then shift the bit
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//Every time WBM says is done, then shift the bit
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//one position
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//one position
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CIRCULAR_SHIFTLEFT_POSEDGE # (4) SHL_A
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CIRCULAR_SHIFTLEFT_POSEDGE # (4) SHL_A
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Enable(iWBMDataAvailable),
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.Enable(iWBMDataAvailable),
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.Reset(~iEnable | Reset ),
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.Reset(~iEnable | Reset ),
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.Initial(4'b1),
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.Initial(4'b1),
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.O(wSelXYZ)
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.O(wSelXYZ)
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vx
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vx
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( ~iEnable | Reset ),
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.Reset( ~iEnable | Reset ),
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.Enable( wSelXYZ[0] & iWBMDataAvailable ),
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.Enable( wSelXYZ[0] & iWBMDataAvailable ),
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.D( iWBMData ),
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.D( iWBMData ),
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.Q( wVx )
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.Q( wVx )
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);
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);
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//The data out is equal to the first vertex that has
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//The data out is equal to the first vertex that has
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//been captured
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//been captured
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assign oData = wVx;
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assign oData = wVx;
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vy
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vy
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( ~iEnable | Reset),
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.Reset( ~iEnable | Reset),
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.Enable( wSelXYZ[1] & iWBMDataAvailable ),
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.Enable( wSelXYZ[1] & iWBMDataAvailable ),
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.D( iWBMData ),
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.D( iWBMData ),
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.Q( wVy )
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.Q( wVy )
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);
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vz
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FFD_POSEDGE_SYNCRONOUS_RESET # (`WIDTH) FFD32_WBMFIFO_Vz
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( ~iEnable | Reset ),
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.Reset( ~iEnable | Reset ),
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.Enable( wSelXYZ[2] & iWBMDataAvailable),
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.Enable( wSelXYZ[2] & iWBMDataAvailable),
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.D( iWBMData ),
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.D( iWBMData ),
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.Q( wVz )
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.Q( wVz )
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);
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);
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assign oDataBus = {wVx,wVy,wVz};
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assign oDataBus = {wVx,wVy,wVz};
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assign oDataWriteEnable = wSelXYZ[3];
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assign oDataWriteEnable = wSelXYZ[3];
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assign oDone = (iStore) ? wSelXYZ[3] : wSelXYZ[1];
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assign oDone = (iStore) ? wSelXYZ[3] : wSelXYZ[1];
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assign oEnableWBM = ~oDone;
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assign oEnableWBM = ~oDone;
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FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_WBMFIFO_V2
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FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD32_WBMFIFO_V2
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D( wSelXYZ[3] ),
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.D( wSelXYZ[3] ),
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.Q(wDelayAfterWriteEnable )
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.Q(wDelayAfterWriteEnable )
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);
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);
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/*
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/*
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always @ (posedge iWBMDataAvailable)
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always @ (posedge iWBMDataAvailable)
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begin
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begin
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$display("%d Got something %h!",$time,iWBMData);
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$display("%d Got something %h!",$time,iWBMData);
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$display("%d Got wSelXYZ %b!",$time,wSelXYZ);
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$display("%d Got wSelXYZ %b!",$time,wSelXYZ);
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end
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end
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*/
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*/
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endmodule
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endmodule
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